Michael S (already5chosen.delete@this.yahoo.com) on August 17, 2020 2:32 am wrote:
> Adrian (a.delete@this.acm.org) on August 17, 2020 1:01 am wrote:
> > Crystal S. Diamond (cdiamond.delete@this.diamondgirls.com) on August 16, 2020 10:20 pm wrote:
> > > Here it is boys...
> > >
> > > https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/53864-ibm-power10-bietet-30-kerne-mit-smt8-pcie-5-und-omi-memory.amp.html?__twitter_impression=true
> >
> >
> >
> > So IBM also jumps on the bandwagon of adding ISA extensions for matrix
> > computations, like NVIDIA, Intel Sapphire Rapids, future ARM etc.
> >
> >
> >

> > New Processor Core Architectures in the IBM POWER10 processor with an embedded Matrix
> > Math Accelerator which is extrapolated to provide 10x, 15x and 20x faster AI inference
> > for FP32, BFloat16 and INT8 calculations per socket respectively than the IBM POWER9
> > processor to infuse AI into business applications and drive greater insights.
> >

> >
> >
>
> IBM appears to do it on FP32 inputs. Is it the case for the rest of them?
> 4x4 FP32 matmul would be useful not just for deep learning.

Page 33 here has a little bit of info on the MMA units. Apparently they can do FP64 as well.

> I wonder why they expose their engine as an outer-product.
> Of course, outer product is very generic, and likely fits well in pipeline
> due to latency, comparable to "normal" FP operations, but it seems to me that
> it makes good FLOPS gains impossible, because of RF write bottleneck.

Yeah, I wonder that too. And what kind of "matrix outer product" is it? Where the inputs are 1-D vectors (for FP64), there is the "usual" matrix outer product, which in that case is equivalent to matrix multiplication with one of the vectors transposed.

When the inputs are 2D matrices, I'm confused. It could be the Kronecker product, but the dimensions in the above page 33 don't match. The dimensions *would* match, if it where normal matrix multiplications.