By: hobold (hobold.delete@this.vectorizer.org), August 18, 2020 2:29 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on August 18, 2020 1:48 pm wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on August 18, 2020 1:00 pm wrote:
[...]
> > I like that centrifuge! It'd be an interesting little design
> > challenge to make something that implements it efficiently.
>
> If I am not mistaken, it's the same as x86 PDEP. On Intel it is reasonably fast (lat=3, thr=1).
> People complained, including on this board, that on AMD it is slow.
> https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=525,3401,4155,2719,4152&othertechs=BMI2
>
PDEP is (half of) the inverse. PEXT is more like it.
The interesting thing about re-arranging a series of values with a stable sort based on a 1 bit key each is this: if the centrifuge is fast enough and wide enough, then it can enable SIMD conditional processing that does not have to follow both sides of the branch. Similar to a GPU programming technique called "stream compaction".
> dmcq (dmcq.delete@this.fano.co.uk) on August 18, 2020 1:00 pm wrote:
[...]
> > I like that centrifuge! It'd be an interesting little design
> > challenge to make something that implements it efficiently.
>
> If I am not mistaken, it's the same as x86 PDEP. On Intel it is reasonably fast (lat=3, thr=1).
> People complained, including on this board, that on AMD it is slow.
> https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=525,3401,4155,2719,4152&othertechs=BMI2
>
PDEP is (half of) the inverse. PEXT is more like it.
The interesting thing about re-arranging a series of values with a stable sort based on a 1 bit key each is this: if the centrifuge is fast enough and wide enough, then it can enable SIMD conditional processing that does not have to follow both sides of the branch. Similar to a GPU programming technique called "stream compaction".
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| "New ISA Prefix Fusion" | Michael S | 2020/08/18 04:48 AM |
| "New ISA Prefix Fusion" | hobold | 2020/08/18 11:58 AM |
| "New ISA Prefix Fusion" | dmcq | 2020/08/18 01:00 PM |
| "New ISA Prefix Fusion" | Michael S | 2020/08/18 01:48 PM |
| "New ISA Prefix Fusion" | hobold | 2020/08/18 02:29 PM |
| "New ISA Prefix Fusion" | Maynard Handley | 2020/08/18 03:46 PM |
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| "New ISA Prefix Fusion" | anon2 | 2020/08/18 07:04 PM |
| "New ISA Prefix Fusion" | Maynard Handley | 2020/08/18 09:17 PM |
| "New ISA Prefix Fusion" | dmcq | 2020/08/19 04:08 AM |
| "New ISA Prefix Fusion" | Maynard Handley | 2020/08/19 10:02 AM |
| "New ISA Prefix Fusion" | dmcq | 2020/08/19 11:08 AM |
| "New ISA Prefix Fusion" | Maynard Handley | 2020/08/19 12:05 PM |
| "New ISA Prefix Fusion" | dmcq | 2020/08/19 02:14 PM |
| "New ISA Prefix Fusion" | Maynard Handley | 2020/08/19 02:44 PM |
| IBM introduces POWER10 | Thu | 2020/08/16 11:56 PM |
| IBM introduces POWER10 | Michael S | 2020/08/17 02:12 AM |
| IBM introduces POWER10 | Thu | 2020/08/17 03:27 AM |
| IBM introduces POWER10 | TransientStudent | 2020/08/17 04:23 AM |
| IBM introduces POWER10 | Rayla | 2020/08/17 04:29 AM |
| IBM introduces POWER10 | Maynard Handley | 2020/08/17 10:44 AM |
| IBM introduces POWER10 | Kevin G | 2020/08/17 10:57 AM |
| IBM introduces POWER10 | Rayla | 2020/08/17 04:26 AM |
| IBM introduces POWER10 | Thu | 2020/08/17 05:00 PM |
| Matrix Math Accelerator | Adrian | 2020/08/17 01:01 AM |
| Matrix Math Accelerator | Michael S | 2020/08/17 02:32 AM |
| Matrix Math Accelerator | Adrian | 2020/08/17 02:46 AM |
| Matrix Math Accelerator | j | 2020/08/18 02:32 AM |
