Michael S (already5chosen.delete@this.yahoo.com) on August 18, 2020 1:48 pm wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on August 18, 2020 1:00 pm wrote:
> > hobold (hobold.delete@this.vectorizer.org) on August 18, 2020 11:58 am wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on August 18, 2020 4:48 am wrote:
> > > [...]
> > > > BTW, Power ISA™ Version 3.1 manual is here https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
> > > >
> > >
> > > Thanks for the link!
> > >
> > > Looks like they are really serious about autovectorization. Quite a few SIMD
> > > bits to round out functionality, and more interoperation between scalar and
> > > SIMD. They even have "vector centrifuge" now ... that is ... interesting.
> >
> > Gah! You can't split a prefixed instruction over a 64 byte boundary.
> > I wonder why they felt it necessary to impose that.
> >
>
> Yes, quite strange, esp. considering that the 1st implementation likely has 128-byte cache lines.

Given what I said (marking pairs in pre-decode) possibly
(a) they want the flexibility (for who knows what future reason) to be able to use 64-byte lines
(b) their 128 lines are implemented as pulling in half a line at a time, critical half first, and they want to be able to predecode that half while they wait on the other half
(c) they want to run two predecoders in parallel on both halves on the line
?


> > I like that centrifuge! It'd be an interesting little design
> > challenge to make something that implements it efficiently.
>
> If I am not mistaken, it's the same as x86 PDEP. On Intel it is reasonably fast (lat=3, thr=1).
> People complained, including on this board, that on AMD it is slow.
> https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=525,3401,4155,2719,4152&othertechs=BMI2
>