By: Michael S (already5chosen.delete@this.yahoo.com), September 18, 2020 5:06 am
Room: Moderated Discussions
Andrei F (andrei.delete@this.anandtech.com) on September 18, 2020 3:39 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on September 18, 2020 2:58 am wrote:
> > anon (anon.delete@this.anon.com) on September 17, 2020 7:10 pm wrote:
> > > AnandTech's (SPEC ST performance) review is here: anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen/8
> > >
> > > All of TigerLake's extra performance over IceLake is due to higher clocks. And it significantly
> > > outperforms the Zen 2 based AMD Renoir chip (Ryzen 7 4800U). However not all is good: TigerLake
> > > experiences a noticeable IPC regression compared to IceLake. The memory subsystem is unable
> > > to keep up with the higher clocks, and the reworked cache is not enough.
> > >
> > > And it just barely beats Apple's A13 despite using significantly more power.
> > > Makes you think the A14 based Mac coming later this year will blow past Intel's
> > > best CPU microarchitecture in single threaded integer performance.
> > >
> > > https://images.anandtech.com/graphs/graph16084/111168.png
> >
> > The picture reminds me of 1951's Arthur C. Clarke classic short story "Superiority".
> >
> >
> > I mean, minimally tweaked 5 y.o. uArch manufactured on maximally
> > tweaked 6 y.o. process reigns on top of the chart.
>
> The difference that you can't see in that chart between the top 3 positions is that
> it's 40W vs 21W vs 4W. The apparent superiority will come crumbling down soon enough.
I suggest to read the story.
The tech of the party that won the war had even bigger disadvantages relatively to to tech of those losing.
> Michael S (already5chosen.delete@this.yahoo.com) on September 18, 2020 2:58 am wrote:
> > anon (anon.delete@this.anon.com) on September 17, 2020 7:10 pm wrote:
> > > AnandTech's (SPEC ST performance) review is here: anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen/8
> > >
> > > All of TigerLake's extra performance over IceLake is due to higher clocks. And it significantly
> > > outperforms the Zen 2 based AMD Renoir chip (Ryzen 7 4800U). However not all is good: TigerLake
> > > experiences a noticeable IPC regression compared to IceLake. The memory subsystem is unable
> > > to keep up with the higher clocks, and the reworked cache is not enough.
> > >
> > > And it just barely beats Apple's A13 despite using significantly more power.
> > > Makes you think the A14 based Mac coming later this year will blow past Intel's
> > > best CPU microarchitecture in single threaded integer performance.
> > >
> > > https://images.anandtech.com/graphs/graph16084/111168.png
> >
> > The picture reminds me of 1951's Arthur C. Clarke classic short story "Superiority".
> >
The ultimate cause of our failure was a simple one: despite all statements to the contrary, it was not
> > due to lack of bravery on the part of our men, or to any fault of the Fleet's. We were defeated by one
> > thing only - by the inferior science of our enemies. I repeat - by the inferior science of our
> > enemies.
> >
> > I mean, minimally tweaked 5 y.o. uArch manufactured on maximally
> > tweaked 6 y.o. process reigns on top of the chart.
>
> The difference that you can't see in that chart between the top 3 positions is that
> it's 40W vs 21W vs 4W. The apparent superiority will come crumbling down soon enough.
I suggest to read the story.
The tech of the party that won the war had even bigger disadvantages relatively to to tech of those losing.
Topic | Posted By | Date |
---|---|---|
Tiger Lake performance profile | anon | 2020/09/17 06:10 PM |
Tiger Lake performance profile | Clipping Coupons | 2020/09/17 07:22 PM |
Tiger Lake performance profile | Doug S | 2020/09/17 09:36 PM |
Tiger Lake performance profile | Jose | 2020/09/18 12:24 AM |
Tiger Lake performance profile | Andrei F | 2020/09/18 02:26 AM |
Tiger Lake performance profile | itsmydamnation | 2020/09/18 02:19 PM |
Tiger Lake performance profile | Maynard Handley | 2020/09/18 04:00 PM |
Tiger Lake performance profile | Andrei F | 2020/09/19 07:29 AM |
Tiger Lake performance profile | Maynard Handley | 2020/09/19 09:34 AM |
Tiger Lake performance profile | Andrei F | 2020/09/19 09:43 AM |
Tiger Lake performance profile | anon | 2020/09/19 10:08 AM |
Tiger Lake performance profile | Andrei Frumusanu | 2020/09/19 10:52 AM |
Tiger Lake performance profile | anon | 2020/09/19 11:50 AM |
Tiger Lake performance profile | Andrei F | 2020/09/19 12:27 PM |
Tiger Lake performance profile | -.- | 2020/09/19 03:31 PM |
Tiger Lake performance profile | Jose | 2020/09/19 01:40 AM |
Tiger Lake performance profile | Andrei F | 2020/09/19 07:25 AM |
Tiger Lake performance profile | Jose | 2020/09/23 12:27 AM |
Tiger Lake performance profile | juanrga | 2020/09/18 01:38 AM |
Tiger Lake performance profile | Doug S | 2020/09/18 08:25 AM |
Tiger Lake performance profile | Andrei F | 2020/09/18 12:04 AM |
Tiger Lake performance profile | Anon | 2020/09/18 02:25 AM |
Tiger Lake performance profile | Andrei F | 2020/09/18 02:31 AM |
Tiger Lake performance profile | Travis Downs | 2020/09/19 07:26 PM |
Tiger Lake performance profile | Michael S | 2020/09/20 09:02 AM |
Tiger Lake performance profile | Travis Downs | 2020/09/20 04:34 PM |
Tiger Lake performance profile | Michael S | 2020/09/21 12:38 AM |
Tiger Lake performance profile | Andrei F | 2020/09/21 05:50 AM |
MKPI ? MPKI ? HPKI ? (NT) | Michael S | 2020/09/21 06:03 AM |
MKPI ? MPKI ? HPKI ? | Anon | 2020/09/21 06:22 AM |
thank you (NT) | Michael S | 2020/09/21 06:42 AM |
MKPI ? MPKI ? HPKI ? | none | 2020/09/22 12:12 AM |
SPEC Memory traffic & bandwidth | Andrei F | 2020/09/21 07:35 AM |
SPEC Memory traffic & bandwidth | Andrei F | 2020/09/21 07:36 AM |
SPEC Memory traffic & bandwidth | David Kanter | 2020/09/21 01:31 PM |
What is the meaning of multiple rows in few subtests? (NT) | Michael S | 2020/09/21 07:45 AM |
What is the meaning of multiple rows in few subtests? | Andrei F | 2020/09/21 07:57 AM |
Poor L1D load bandwidth | Eric Bron | 2020/09/21 05:56 AM |
erratum | Eric Bron | 2020/09/21 05:59 AM |
Sorry I missread the graph | Eric Bron | 2020/09/21 06:14 AM |
Poor main memory load bandwidth | Michael S | 2020/09/21 06:19 AM |
Tiger Lake performance profile | Travis Downs | 2020/09/21 02:51 PM |
Tiger Lake performance profile | Andrei F | 2020/09/22 06:03 AM |
Tiger Lake security fixes possible cause? | Kevin G | 2020/09/22 05:10 AM |
Tiger Lake security fixes possible cause? | Travis Downs | 2020/09/22 06:26 AM |
Superiority | Michael S | 2020/09/18 01:58 AM |
Superiority | Andrei F | 2020/09/18 02:39 AM |
Superiority | Robert Müller | 2020/09/18 02:59 AM |
Superiority | Andrei F | 2020/09/18 03:47 AM |
Superiority | Robert Müller | 2020/09/18 04:45 AM |
Superiority | Andrei F | 2020/09/18 05:17 AM |
Superiority | Travis Downs | 2020/09/18 06:21 AM |
Superiority | anon | 2020/09/18 11:34 AM |
Superiority | Michael S | 2020/09/18 05:06 AM |
Superiority | Foo_ | 2020/09/18 05:17 AM |
Superiority | Michael S | 2020/09/18 06:08 AM |
Superiority | David Hess | 2020/09/18 11:55 AM |
Superiority | Adrian | 2020/09/18 04:56 AM |
Superiority | Michael S | 2020/09/18 06:51 AM |
Superiority | Adrian | 2020/09/18 08:35 AM |
Superiority | thePirate | 2020/09/19 01:28 AM |