Travis Downs (travis.downs.delete@this.gmail.com) on September 20, 2020 5:34 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on September 20, 2020 10:02 am wrote:
> > Travis Downs (travis.downs.delete@this.gmail.com) on September 19, 2020 8:26 pm wrote:
> > > Andrei F (andrei.delete@this.anandtech.com) on September 18, 2020 1:04 am wrote:
> > > > anon (anon.delete@this.anon.com) on September 17, 2020 7:10 pm wrote:
> > > > > AnandTech's (SPEC ST performance) review is here: anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen/8
> > > > > However not all is good: TigerLake
> > > > > experiences a noticeable IPC regression compared to IceLake. The memory subsystem is unable
> > > > > to keep up with the higher clocks, and the reworked cache is not enough.
> > > > >
> > > >
> > > > I just want to add on that sentence as that's not what I wrote
> > > > in the piece: I don't think the memory subsystem is to blame.
> > > >
> > > > It's significantly stronger than ICL and showcases *much* better DRAM latency and significant
> > > > single core bandwidth uplift. 429.mcf showcases great scaling well beyond clocks, showing
> > > > that latency for example is not to blame. In my opinion it's a regression *because* of the
> > > > reworked cache, as essentially the L3 is now 20% slower per clock versus ICL.
> > >
> > > You mean L3 latency, right? It might be a part of it, but the regression in libquantum
> > > and lbm are too large to be explained by this few cycle change, I think. You'd pretty much
> > > have to write a dedicated L3 latency test to get that big of a drop and IIRC neither of
> > > those are known to be very dependent on L3 latency (they are more bandwidth heavy).
> > >
> > > So I think there's something else more interesting going on there.
> > >
> > >
> >
> > TGL uncore appears to be inspired SKX, except, hopefully, better latency of LLC misses under light load.
> > So, may be, it suffers from similarly low single-core bandwidth?
> >
>
> Well Andrei has some detailed bandwidth benchmarks on this page and performance looks
> better across the board: there's actually a significant bump in L3 and RAM regions.
>

Yes, it's better than ICL.
But probably quite a lot worse than desktop SKL. Out of memory ( :-) ), my E-2176G achieves 33-35 GB/s on long sequential reads, supposedly similar to Andrei's Vec128 LD test. If I am not mistaken, even i7-6920HQ with DDR4-2133 that I was playing with couple of years ago, was capable to do 30 GB/s. From raw bandwidth perspective LPDDR4X-4266 in TGL rig should be equal to DDR4-2133, right? But the end result is somehow 1.5x lower.
I have no idea what "flip" tests do, so can't compare.

> So I feel like it has to be something more complicated than just worse peak BW: maybe a different
> way of splitting power between core, uncore and memory? Paul Alcorn from Tomshardware suggested
> that memory frequency itself can be varied on this part, not sure if that's correct. I don't
> think any previous Intel part had frequency scaling for the memory bus?
>