Tiger Lake security fixes possible cause?

By: Travis Downs (travis.downs.delete@this.gmail.com), September 22, 2020 6:26 am
Room: Moderated Discussions
Kevin G (kevin.delete@this.cubitdesigns.com) on September 22, 2020 6:10 am wrote:
> Andrei F (andrei.delete@this.anandtech.com) on September 18, 2020 1:04 am wrote:
> > anon (anon.delete@this.anon.com) on September 17, 2020 7:10 pm wrote:
> > > AnandTech's (SPEC ST performance) review is here: anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen/8
> > > However not all is good: TigerLake
> > > experiences a noticeable IPC regression compared to IceLake. The memory subsystem is unable
> > > to keep up with the higher clocks, and the reworked cache is not enough.
> > >
> >
> > I just want to add on that sentence as that's not what I wrote
> > in the piece: I don't think the memory subsystem is to blame.
> >
> > It's significantly stronger than ICL and showcases *much* better DRAM latency and significant
> > single core bandwidth uplift. 429.mcf showcases great scaling well beyond clocks, showing
> > that latency for example is not to blame. In my opinion it's a regression *because* of the
> > reworked cache, as essentially the L3 is now 20% slower per clock versus ICL.
> One thing Intel certainly has been improving is there security due various exploits and side channel
> attacks that have appeared over the past couple of years. Looking at the time line, especially
> factoring in Intel's knowledge prior to public disclosure, Tiger Lake would be the first chip to
> have the fixes in place that required significant alterations to the design. An example would be
> some of the bypass networks being removed or having extra logic added to them to enhance security.
> While not explicitly written to use them, the algorithms used by SPEC could have been an optimal
> fit for using them in the design. For Tiger Lake, what used to be optimal is not nearly as much
> or the gains provided by the bypass network are not as significant as they used to be.

It is not impossible but I think it is unlikely. I can't think of any version of the side channel issues that would have a particularly expensive hardware-only fix. They either have cheap fixes (usually very cheap), or can't really be fixed and basically being ignored.

There is another category of stuff where the fix is some combination of hardware support and software changes (e.g., special MSRs to flush structures), and here newer chips are usually getting faster as the hardware side of the support gets better.

SKX had quite poor performance in the "middle" of the memory hierarchy (around L3) for ST loads (I measured 6 bytes/cycle bandwith or something like that), so it is not that strange that perhaps TGL, which superficially shares some SKX characteristics, might have inherited some of those tradeoffs.

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TopicPosted ByDate
Tiger Lake performance profileanon2020/09/17 06:10 PM
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  Tiger Lake performance profileDoug S2020/09/17 09:36 PM
    Tiger Lake performance profileJose2020/09/18 12:24 AM
      Tiger Lake performance profileAndrei F2020/09/18 02:26 AM
        Tiger Lake performance profileitsmydamnation2020/09/18 02:19 PM
          Tiger Lake performance profileMaynard Handley2020/09/18 04:00 PM
            Tiger Lake performance profileAndrei F2020/09/19 07:29 AM
              Tiger Lake performance profileMaynard Handley2020/09/19 09:34 AM
                Tiger Lake performance profileAndrei F2020/09/19 09:43 AM
                  Tiger Lake performance profileanon2020/09/19 10:08 AM
                    Tiger Lake performance profileAndrei Frumusanu2020/09/19 10:52 AM
                      Tiger Lake performance profileanon2020/09/19 11:50 AM
                        Tiger Lake performance profileAndrei F2020/09/19 12:27 PM
          Tiger Lake performance profile-.-2020/09/19 03:31 PM
        Tiger Lake performance profileJose2020/09/19 01:40 AM
          Tiger Lake performance profileAndrei F2020/09/19 07:25 AM
            Tiger Lake performance profileJose2020/09/23 12:27 AM
    Tiger Lake performance profilejuanrga2020/09/18 01:38 AM
      Tiger Lake performance profileDoug S2020/09/18 08:25 AM
  Tiger Lake performance profileAndrei F2020/09/18 12:04 AM
    Tiger Lake performance profileAnon2020/09/18 02:25 AM
      Tiger Lake performance profileAndrei F2020/09/18 02:31 AM
    Tiger Lake performance profileTravis Downs2020/09/19 07:26 PM
      Tiger Lake performance profileMichael S2020/09/20 09:02 AM
        Tiger Lake performance profileTravis Downs2020/09/20 04:34 PM
          Tiger Lake performance profileMichael S2020/09/21 12:38 AM
            Tiger Lake performance profileAndrei F2020/09/21 05:50 AM
              MKPI ? MPKI ? HPKI ? (NT)Michael S2020/09/21 06:03 AM
                MKPI ? MPKI ? HPKI ?Anon2020/09/21 06:22 AM
                  thank you (NT)Michael S2020/09/21 06:42 AM
                  MKPI ? MPKI ? HPKI ?none2020/09/22 12:12 AM
              SPEC Memory traffic & bandwidthAndrei F2020/09/21 07:35 AM
                SPEC Memory traffic & bandwidthAndrei F2020/09/21 07:36 AM
                  SPEC Memory traffic & bandwidthDavid Kanter2020/09/21 01:31 PM
                What is the meaning of multiple rows in few subtests? (NT)Michael S2020/09/21 07:45 AM
                  What is the meaning of multiple rows in few subtests?Andrei F2020/09/21 07:57 AM
            Poor L1D load bandwidthEric Bron2020/09/21 05:56 AM
              erratumEric Bron2020/09/21 05:59 AM
              Sorry I missread the graphEric Bron2020/09/21 06:14 AM
              Poor main memory load bandwidthMichael S2020/09/21 06:19 AM
            Tiger Lake performance profileTravis Downs2020/09/21 02:51 PM
              Tiger Lake performance profileAndrei F2020/09/22 06:03 AM
    Tiger Lake security fixes possible cause?Kevin G2020/09/22 05:10 AM
      Tiger Lake security fixes possible cause?Travis Downs2020/09/22 06:26 AM
  SuperiorityMichael S2020/09/18 01:58 AM
    SuperiorityAndrei F2020/09/18 02:39 AM
      SuperiorityRobert Müller2020/09/18 02:59 AM
        SuperiorityAndrei F2020/09/18 03:47 AM
          SuperiorityRobert Müller2020/09/18 04:45 AM
            SuperiorityAndrei F2020/09/18 05:17 AM
              SuperiorityTravis Downs2020/09/18 06:21 AM
          Superiorityanon2020/09/18 11:34 AM
      SuperiorityMichael S2020/09/18 05:06 AM
        SuperiorityFoo_2020/09/18 05:17 AM
          SuperiorityMichael S2020/09/18 06:08 AM
      SuperiorityDavid Hess2020/09/18 11:55 AM
    SuperiorityAdrian2020/09/18 04:56 AM
      SuperiorityMichael S2020/09/18 06:51 AM
        SuperiorityAdrian2020/09/18 08:35 AM
          SuperioritythePirate2020/09/19 01:28 AM
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