hobold (hobold.delete@this.vectorizer.org) on October 10, 2020 12:19 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on October 10, 2020 10:36 am wrote:
> > hobold (hobold.delete@this.vectorizer.org) on October 10, 2020 8:58 am wrote:
>
> [...]
> > > But one cannot reduce latency below zero (no matter what marketing departments
> > > say), so these gains are not very likely to be repeated by AMD.
> >
> > Yes you can :-) Value prediction is real, and done competently provides genuine speedups...
> > As far as I can tell no-one is doing value prediction yet (as always asterisk against Apple...)
> > but it's still a promising technology once everything easier has been done.
>
> Latency is the time you must wait for an unknown result that will be produced in the future.
> Value prediction is re-use of a known result that has been produced in the past.
>
> It is possible to try and guess the future. It is not commonly possible
> to reliably violate causality (in the macroscopic world).
>
> I do not mean to diminish all the ingenious speculative algorithms. But for the benefit of the lurking
> readers, I want to re-iterate that latency times are always strictly greater than zero.
>
> No matter what marketing departments or internet discussion forums say. :-)

Value prediction may predict previously unknown values, much like prefetchers can predict unknown addresses (e.g., Stride prefetcher and its counterpart Stride value predictor). In practice those "unseen before" values may well be addresses (or values feeding address generation e.g., loop induction variable) that the prefetcher would have gotten too.

You might be thinking about instruction reuse which is a different thing : Sodani et al., "Understanding the differences between value prediction and instruction reuse" at MICRO 1998 http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15740-f02/public/doc/discussions/uniprocessors/value_pred/vp_vs_ir_micro98.pdf

On latency, I would contend that in isolation, latency is always greater than 0 because you have to at least fetch the instruction. However with superscalar and OoO the latency of some instructions does not appear on the critical path. Moreover, for instructions that *do* appear on the critical path, superscalar fetch + some optimizations (move elimination, zero/one-idiom elimination and now memory bypassing) can cause instructions to appear has having 0 latency.