Zen 3

By: anon (anon.delete@this.ymous.org), October 11, 2020 12:07 pm
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on October 11, 2020 12:32 pm wrote:
> anon (anon.delete@this.ymous.org) on October 11, 2020 2:58 am wrote:
> [...]
> > Value prediction may predict previously unknown values, much like prefetchers can predict
> > unknown addresses (e.g., Stride prefetcher and its counterpart Stride value predictor).
> > In practice those "unseen before" values may well be addresses (or values feeding address
> > generation e.g., loop induction variable) that the prefetcher would have gotten too.
> >
> The words "unseen before" mean something other than "unknown". Just like "prediction"
> does not mean the same as accurately foretelling the actual future.
> [...]
> > On latency, I would contend that in isolation, latency is always greater than 0 because you have
> > to at least fetch the instruction. However with superscalar and OoO the latency of some instructions
> > does not appear on the critical path. Moreover, for instructions that *do* appear on the critical
> > path, superscalar fetch + some optimizations (move elimination, zero/one-idiom elimination and
> > now memory bypassing) can cause instructions to appear has having 0 latency.
> The word "appear" means something other than "be".
> I am splitting hairs here. I get that I may appear to be hell-bent on having the final word on this.
> But I hate it when engineers begin to think in concepts that are rooted more in marketing than in
> observable phenomena. Knowing the future beforehand is possible only under very specific circumstances.
> Negative latency is possible only with the help of a time machine (in the macroscopic world). Thinking
> in incorrect terminology misleads the thinkers to make blatant mistakes.
> Take my favourite example from recent history: the retire stage of a microprocessor.
> Its function and purpose is to create the limited appearance of strictly sequential
> program execution, despite the reality of dynamic out of order execution.
> If one's mental concept is that the retire stage creates anything more than a limited appearance, then one might
> be tempted to implement further functionality in that same pipeline stage. If this line of thought ever leads
> to the implementation of security features in the retire stage ("we can remove this from the critical path!"),
> then one ends up with a processor that creates the limited appearance of security. A very real meltdown.

Sure, appear is different than "be". Performance wise, "appear" is enough, however, and value prediction is a performance feature (which will have to be made Spectre-proof). I don't think anyone mentioned negative latency, merely 0-latency. What difference do you make between "unseen before" and "unknown"?
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