> The die size for an FPGA that can make good use of the IF bandwidth and do something
> worth replacing a CPU chiplet with is going to be a fair bit bigger than the CPU chiplet
> I think. The Rome package is already pretty full, so I think you'd probably need to
> sacrifice multiple chiplets, probably even half of them to make it work.
>
> It might be more practical, particularly in the short term to allow pairing a specially packaged
> FPGA with a normal CPU in a 2-socket system, using the FPGA transceivers to implement the inter-chip
> variant of Infinity Fabric and also supporting the existing DRAM slots. For the very short term
> you could also do PCIe between sockets as well, although then you loose cache coherencey.

Past attempts by AMD and Intel weren't exactly stunning commercial successes.

The term "solution looking for a problem" comes to mind, to be honest.