AMD - Xilinx merger. Potential technical synergies?

By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), October 31, 2020 5:46 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on October 31, 2020 9:53 am wrote:
> Ricardo B (ricardo.b.delete@this.xxxxx.xx) on October 30, 2020 7:02 pm wrote:
> > Rob Thorpe (noone.delete@this.nowhere.com) on October 28, 2020 12:40 pm wrote:
> >
> > > Xilinx FPGAs are RAM based FPGAs. They're mostly made out of many copies of the same simple blocks. The
> > > most common of those are similar to RAM. Because of this,
> > > those simple parts of them can be tailored closely
> > > to a process. Microprocessor companies like AMD do effectively the same thing with their cache RAM.
> > >
> > > There's the possibility to save on R&D costs here, since the products are at least fairly
> > > similar. For a long time FPGAs have been launched on fairly cutting-edge processes. Quite
> > > often they have been nearly as cutting-edge as microprocessors. I don't know enough about
> > > this part of the industry to be sure. Perhaps someone who does can chime in.
> >
> > Uh. 50-50%
> >
> > Xilinx FPGAs being SRAM based just means they're made of tons (few tens of K
> > to few M) of tiny blocks containing a 16-64 bit SRAM plus some extra logic.
> > These have nothing to do with the much larger (hundreds kbit) SRAM blocks found in CPU caches.
> > Performance targets are also nowhere near close to those of CPUs.
> >
>
> 7 Series FPGAs also has (5 to ~2000) 36kbit Block RAM blocks which are pure SRAM.
> Still smaller, I suppose, than L2 or L3 cache blocks of Zen, but not completely dissimilar.
> You can rightly say that Block RAM occupies only 5 or 10% of the total chip area, but in CPUs
> caches also are not the most area-consuming parts. More that 10% but probably less than 20%.

True.
But they're also much slower than CPU cache SRAM.

>
> > On the other hand FPGAs are indeed uniquely suited to be an early product on a new process.
> > A state of the art ASIC/CPU/GPU/etc will require the process
> > to be well under control and for hundreds (thousands?)
> > of cell variants to be designed and carefully characterized before a chip goes into production.
> > Any safety margin will be locked in the design and to reap most of the benefits of better
> > process control or better characterization will require a respin of the chip.
> >
>
> I am not sure that it makes sense economically for FPGA company to become an early adapter of the
> new process. Very new chips are tiny part of the revenue, so why overpay for their production?
> It seems, typically FPGAs start to ship production parts on the process that is 1-1.5 years old.
> With likes of Apple overpaying for new stuff, may be, by now it should e closer to 2 years.

I haven't kept track meanwhile but for example the 28 nm Kintex-7 shipped some 2 years before Qualcomm and Apple's 28 nm SoC.
The 16 nm Kintex UltraScale+ seems have trailed Apple's 16 nm SoC by about 3 months.

On one hand the FPGA part in the FPGAs greatly benefit of smaller process nodes (eg, power)

On the other hand it's not clear to me they were overpaying.
It's also on the foundry's interest to offer good terms to this client which will likely be ready to enter production while most of your clients are still doing engineering runs and demanding process improvements.
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TopicPosted ByDate
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