Doug S (foo.delete@this.bar.bar) on November 18, 2020 7:44 am wrote:
>
> If so, then the only argument is that 4 big cores WITH SMT along with 4 little cores is faster
> than 4 big cores without SMT and 4 little cores. Which is obvious, but then you could add 4
> more little cores, or one more big core, to reach that level of performance without all the
> extra design/verification/security headaches of SMT. Before someone says "but that costs more
> because the die is bigger", yes, but we're talking about increasing the M1's die size maybe
> 3% - and for something that will benefit ALL MT loads, not just the ones are helped by SMT.

Oh, the die size argument. Well if adding a core costs so little, why didn't Apple already do it?
It's usually a bit more complex.
BTW, Intel seems to have done it your way on Alder Lake. Instead of going say 10 big cores, they went for 8 big and 8 small. The small cores are likely in 4c clusters I expect, so they sub two big ones.
But, Intel still kept HT on the big cores. Apparently it turns out to still be better that way.