Maynard Handley (name99.delete@this.name99.org) on November 18, 2020 1:12 pm wrote:
> David Hess (davidwhess.delete@this.gmail.com) on November 18, 2020 12:12 pm wrote:
> > Maynard Handley (name99.delete@this.name99.org) on November 18, 2020 8:37 am wrote:
> > >
> > > SMT is a decision to swap something that is cheap and plentiful (space for an *independent*
> > > core on the die) with something that is expensive and in extremely short supply (the SRAM
> > > that feeds the predictors and caches that give you all that IPC for a particular core).
> > >
> > > Explain to me why that is a sensible tradeoff...
> >
> > SMT is a decision to swap something that is expensive and in extremely short supply (power
> > hungry logic) with something that is cheap and plentiful (low power SRAM and state).
>
> Logic is only power hungry if you're doing it incorrectly.
>
> If state (appropriately configured...) is so cheap then (to give an obvious example) why don't AMD and Intel
> copy Apple's monster sized caches? That really is the essence of it. You can't simultaneously argue that
> Apple is getting some sort of "unfair advantage" by having very large caches AND that it would a good design
> decision for Apple to run its cores in a way that halves the effective size of those caches.

Who says Intel and AMD have not? I had not noticed that cache sizes, especially level 3 cache, had not increased. Intel extensively uses cache size for market segmentation. Lower level caches are limited in size because of performance reasons.

Back when RISC workstations and the death of x86 might have been considered a possibility, MIPS was asked about what they would do when millions (!) of transistors were available in a couple of generations and they answered, "add more cache." MIPS dropped out of the workstation market not long after that.

If Apple is designing for a lower power target than Intel and AMD, then their designs should have a higher ratio of cache to logic.