dmcq (dmcq.delete@this.fano.co.uk) on November 20, 2020 4:37 am wrote:
> Andrei F (andrei.delete@this.anandtech.com) on November 20, 2020 12:47 am wrote:
> > Maynard Handley (name99.delete@this.name99.org) on November 19, 2020 8:22 pm wrote:
> > > OK guys, M1 time is over. What's next?
> > >
> > > Something I just realized, and I think the timing works out beautifully:
> > > TSMC started N5P testing/Risk production in 2Q2020.
> > > Meaning that (and now that I think about it, it is so obvious!) the M1X will be on N5P!
> > > THAT is what's determining its schedule.
> > >
> > > There is a precedent. Remember that the A10 came out in Sept
> > > 2016, on 16nm. But the A10X came out in June 2017 on 10nm.
> > >
> > > This makes so much sense. It gives time Apple to improve some of the rushed bits of the M1, and gives
> > > a free 5% speed boost (which isn't much, sure, but may mean that M1X clocks at, say 3.5GHz)
> > > And gives Apple a second round of (totally justified!) "OMG,
> > > Apple is king, everyone else is doomed" publicity,
> > > say maybe in April or May, which should sustain them till the A15/iPhone next reveals in September.
> > >
> > > Well, six months or so to see if I'm right. tick tick tick
> >
> > 8 big core piece is next, timing isn't clear but I suppose next 6-8 months.
>
> And as your article in Anandtech shows there' some obvious things which they can
> improve like the multi-core memory performance.

Sorry what? They are destroying everybody in MT memory perf within that core-count.

If you mean those initial copy results, I had removed that paragraph, it's because the large cores detected the streams and turned them into nontemporal transfers, the little cores don't have that ability and that's why when they got added in the bandwidth appeared to reduce, as it turned into your classical 2R1W traffic behaviour. Using explicit non-temporal copies flatlines at 59GB/s across all cores.