anon2 (anon.delete@this.anon.com) on November 19, 2020 8:59 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on November 19, 2020 8:22 pm wrote:
> > OK guys, M1 time is over. What's next?
> >
> > Something I just realized, and I think the timing works out beautifully:
> > TSMC started N5P testing/Risk production in 2Q2020.
> > Meaning that (and now that I think about it, it is so obvious!) the M1X will be on N5P!
> > THAT is what's determining its schedule.
> >
> > There is a precedent. Remember that the A10 came out in Sept
> > 2016, on 16nm. But the A10X came out in June 2017 on 10nm.
> >
> > This makes so much sense. It gives time Apple to improve some of the rushed bits of the M1,
>
> What bits of M1 are rushed? What's your basis for saying that? This is a derivative
> core of a now very solid core microarchitecture. Does their new hypervisor implementation
> have bad errata, or their x86 emulation sub-par, or something?

Physical Optimization looks rushed. In the sense that the density is nothing close to what N5 is capable of (and what is achieved by Kirin).
You can argue this is because of some inherent choice by Apple to use more relaxed layout and larger cells, but that makes no sense on historical grounds or performance grounds. I think it's just that they didn't have time to do the full POPT that they've always been able to do before.