James (no.delete@this.thanks.invalid) on November 21, 2020 7:18 am wrote:
> Brett (ggtgp.delete@this.yahoo.com) on November 20, 2020 8:56 pm wrote:
>
> > But to go wider x86 decoding becomes expensive in area and
> > heat. x86 is stuck between a rock and a hard place, something has to give.
>
> Two obvious routes are keeping the decoder much as it is and making the L0 cache and
> the rest of the core wider, and adding decode hints to the L1 instruction cache.

Half the difference between Apple M1 and Intel may be 8 wide fetch of cold code.

You also have the issue that Apple is going fully 8 wide, you can’t do that with a 5GHz fireball.

To support a 8 wide pipeline you need 10-12 wide fetch, which rounds up to 16 wide fetch.

X86 decode is doomed.

> You could do either of those without breaking compatibility -- so history
> implies both Intel and AMD would want to do so if it was practical.