Andrey (andrey.semashev.delete@this.gmail.com) on November 27, 2020 7:56 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on November 27, 2020 3:34 am wrote:
> >
> > IMHO, the correct question is "Why force zeros to main DRAM at all?".
> > What's wrong with zeroing page in cache and relaying on normal cache evictions for taking care of the rest?
>
> Perhaps to avoid wasting cache space and traffic for zeroing. I suspect, that's one reason to do it using
> non-temporal stores instead of regular stores. You could potentially use AVX-512 for this to align stores
> to a cache line. AMD has CLZERO, although it's not supposed to be used for regular zeroing memory.
>
> However, I think an ideal solution should be a custom command to the DRAM chips from the memory controller
> to fill a region with a specified value, issued as a result of a dedicated instruction. If the affected
> memory is already in cache, these cache lines are invalidated. This would save some traffic between
> the memory controller and DRAM, and as a result would probably save some power. I'm not sure if this
> would offer any performance improvements or how complicated it would be to implement.
>

DDR5 starts down that road - while you still have to issue sufficient writes, there are special write pattern commands that you can use for write all zeroes. At the moment, these only save you driving the data lines (the command is supposed to trigger the DRAM setting the data lines directly), thus saving power, but there's no reason that the DRAM couldn't do more over time.