80x86 Instruction Alignment Hint?

By: Brendan (btrotter.delete@this.gmail.com), November 30, 2020 11:29 pm
Room: Moderated Discussions
A silly thought...

Can Intel or AMD define a new flag in EFLAGS, and create 2 new "set/clear that flag" instructions that will be ignored (treated as NOP) on older CPUs (similar to the way PAUSE was added)?

On newer/future CPUs; when that new flag is set; can Intel or AMD expect that all instructions are aligned to an 8-byte boundary (and padded with NOPs if they're actually shorter); and disable the traditional decoder and enable a new alternative "fixed instruction length" decoder?

In other words; can 80x86 switch to fixed length instructions in a fully backward compatible way?
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TopicPosted ByDate
80x86 Instruction Alignment Hint?Brendan2020/11/30 11:29 PM
  maybe but why? (NT)anonymous22020/12/01 12:00 AM
    Performance vs M1?Brendan2020/12/01 12:32 AM
      Performance vs M1?Chester2020/12/01 12:49 AM
        Performance vs M1?Will2020/12/01 12:53 AM
          Performance vs M1?anon2020/12/01 01:13 AM
            Performance vs M1?Wilco2020/12/01 05:47 AM
              Performance vs M1?anon2020/12/01 10:42 AM
                Performance vs M1?Foo_2020/12/01 01:17 PM
        Performance vs M1?anon2020/12/01 01:32 AM
        Performance vs M1?A.K.2020/12/01 01:42 AM
          About widthChester2020/12/01 02:51 AM
            About widthnone2020/12/01 04:35 AM
              About widthChester2020/12/01 06:08 AM
                About widthnone2020/12/01 08:15 AM
                  About widthChester2020/12/01 11:33 PM
                    About widthnone2020/12/02 12:46 AM
                About widthBrett2020/12/01 02:38 PM
                Talking about single width number makes NO sense with OoOE cores (NT)Heikki Kultala2020/12/02 01:58 AM
                  Talking about single width number makes NO sense with OoOE coresChester2020/12/02 11:42 AM
                    Talking about single width number makes NO sense with OoOE coresanon2020/12/03 12:15 PM
                      Talking about single width number makes NO sense with OoOE coresChester2020/12/03 02:00 PM
                        This meaningless discussion perfectly proves my point. It makes no sense to try to sinplify it to s (NT)Heikki Kultala2020/12/03 05:47 PM
            About width / Memory trafficTim McCaffrey2020/12/01 08:53 AM
              About width / Memory trafficChester2020/12/01 12:00 PM
                About width / Memory trafficTim McCaffrey2020/12/01 01:51 PM
                  About width / Memory trafficChester2020/12/01 07:25 PM
          Performance vs M1?Simon Farnsworth2020/12/01 05:41 AM
        You don't seem to understand OoO executionWilco2020/12/01 06:30 AM
          You don't seem to understand OoO executionDoug S2020/12/01 10:10 AM
            You don't seem to understand OoO executionChester2020/12/01 11:16 AM
              You don't seem to understand OoO executionWilco2020/12/01 02:46 PM
                You don't seem to understand OoO executionChester2020/12/01 11:11 PM
      Performance vs M1?anon2020/12/01 01:19 AM
        Performance vs M1?Jan Vlietinck2020/12/01 02:33 AM
          Performance vs M1?Chester2020/12/01 02:58 AM
            Performance vs M1?Jan Vlietinck2020/12/01 03:20 AM
              Performance vs M1?Chester2020/12/01 03:31 AM
                Performance vs M1?Jan Vlietinck2020/12/01 05:13 AM
                  Performance vs M1?Wilco2020/12/01 07:03 AM
                    Modern RISC: VLE, index+offset addressing, multicycle opsPaul A. Clayton2020/12/01 09:43 AM
                    On overcoming some of the CISC limitations2020/12/01 11:41 AM
                      On overcoming some of the CISC limitationsanon2020/12/01 11:58 AM
                        On overcoming some of the CISC limitations2020/12/02 09:41 AM
                    RISC addressing modesHeikki Kultala2020/12/02 02:04 AM
                      RISC addressing modesWilco2020/12/02 09:33 AM
                        RISC addressing modesanon2020/12/03 12:10 PM
              Performance vs M1?Wilco2020/12/01 06:55 AM
                Performance vs M1?Jan Vlietinck2020/12/01 07:19 AM
                  Performance vs M1?Wilco2020/12/01 09:31 AM
              Performance vs M1?juanrga2020/12/02 05:12 AM
              Performance vs M1?dmcq2020/12/02 06:57 AM
                RISC is about the ISA, not implementationWilco2020/12/02 07:39 AM
                  RISC is about the ISA, not implementationdmcq2020/12/02 10:57 AM
                     AArch64 marketing failureanon2020/12/02 11:17 AM
                    RISC is about the ISA, not implementationAndrew Clough2020/12/02 11:22 AM
                    RISC is about the ISA, not implementationWilco2020/12/02 12:14 PM
                    the meaning of 'R'incorrector2020/12/02 03:03 PM
                      the meaning of 'R'Brett2020/12/02 05:16 PM
                        the meaning of 'R'incorrector2020/12/02 07:54 PM
                        the meaning of 'R'dmcq2020/12/03 06:49 AM
                Performance vs M1?Jan Vlietinck2020/12/03 05:44 AM
  80x86 Instruction Alignment Hint?tyututyu2020/12/01 05:45 AM
  80x86 Instruction Alignment Hint?Andrey2020/12/02 04:23 AM
    80x86 Instruction Alignment Hint?Brendan2020/12/02 06:45 PM
  80x86 Instruction Alignment Hint?2020/12/02 01:41 PM
    80x86 Instruction Alignment Hint?Brendan2020/12/02 07:00 PM
      80x86 Instruction Alignment Hint?2020/12/03 02:34 AM
        80x86 Instruction Alignment Hint?2020/12/03 02:38 AM
        80x86 Instruction Alignment Hint?Brendan2020/12/03 06:18 AM
          80x86 Instruction Alignment Hint?2020/12/06 02:04 AM
        80x86 Instruction Alignment Hint?NoSpammer2020/12/03 08:03 AM
          80x86 Instruction Alignment Hint?Chester2020/12/03 03:20 PM
          80x86 Instruction Alignment Hint?2020/12/06 03:03 AM
            80x86 Instruction Alignment Hint?Brett2020/12/06 12:22 PM
              80x86 Instruction Alignment Hint?2020/12/07 09:01 AM
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