Enough with the idiocy ... let's have proper ECC again.

By: Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com), December 17, 2020 7:41 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on December 17, 2020 12:04 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on December 17, 2020 9:42 am wrote:
> > Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on December 17, 2020 9:26 am wrote:
> > > Maynard Handley (name99.delete@this.name99.org) on December 17, 2020 9:09 am wrote:
> > > > Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com) on December 16, 2020 10:09 pm wrote:
> > > > > Adrian (a.delete@this.acm.org) on December 16, 2020 7:31 am wrote:
> > > > > > Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on December 15, 2020 3:24 pm wrote:
> > > > > > > It seems like Intel has added support for what they call in-band ECC to their recent Atom SoCs, see the
> > > > > > > mention here as well as here. There isn't much in the way of details on Intel pages apart from the
> > > > > > > fact that the mechanism can correct single-bit errors in
> > > > > > > non-ECC memory (presumably by reducing its effective
> > > > > > > size). However a Google search turned out this patent. All-in-all a very welcome development.
> > > > > >
> > > > > >
> > > > > > The support for In-Band ECC also exists in Tiger Lake U, but it is disabled in almost all SKUs,
> > > > > > including in most of the "Embedded" SKUs, where I would have expected it to be enabled.
> > > > > >
> > > > > > It is enabled only in the Tiger Lake U "Embedded" SKUs for the Extended Temperature Range.
> > > > > >
> > > > > > In-Band ECC allows the use of ECC with the LPDDR4x memories, but this advantage is paid
> > > > > > by a slight reduction in memory capacity and by a reduction in speed that is difficult to
> > > > > > quantify, because in most cases the extra accesses for ECC can be cached (the worst but
> > > > > > very seldom case is to do twice as many memory accesses, both for data and for ECC).
> > > > > >
> > > > > >
> > > > > > Intel has a patent application for it
> > > > >
> > > > > The padawans here may not know that back in the day, even after they were born, it was
> > > > > as simple as pie to order simms and dimms with parity/ecc at little additional cost.
> > > > >
> > > > > Sure, if you didn't care about ECC you could shave off a few percentage points on
> > > > > the price of memory. Big deal, but not for everybody, I'd always go for the slightly
> > > > > more expensive option (at least I could use it in system that supported it).
> > > > >
> > > > > Then something happened which changed the DRAM landscape forever (hopefully not forever though).
> > > > > What happened? Intel started producing processors that had no, absolutely no, nada, ability to implement
> > > > > ECC. These CPUs have for the last two decades been by far the bulk of processors sold. Could you
> > > > > have undetected memory errors? Yes, it's a near certainty. Could these have had serious consequences?
> > > > > Hard to say, are you working on anything that could have serious consequences?
> > > > >
> > > > > At a guess, an ECC capable DIMM costs 5-9% more to get to an end user than one that is
> > > > > without ECC. I'm willing to pay more than that for such a "fancy" feature, but oh-no, it's
> > > > > nearly impossible to source un-buffered ECC ram at reasonable speeds and/or prices.
> > > > >
> > > > > This in-line ECC appears to be a colossal kludge, presented as
> > > > > a feature, to solve a problem that never should have existed.
> > > > >
> > > > > > https://www.freepatentsonline.com/y2019/0332469.html
> > > > > >
> > > > > > which should have been rejected, because it describes good methods to implement
> > > > > > In-Band ECC, but which are completely obvious and are exactly like anyone would
> > > > > > implement it if given the task, without any other prior knowledge.
> > > > >
> > > > >
> > > >
> > > > From the startup log on an M1 boot...
> > > > 10.281418 AppleFireStormErrorHandler AppleARM64ErrorHandler: will not panic on correctible ECC errors
> > > >
> > >
> > > That is nice not to panic on correctible ECC error (instead
> > > of panic-ing, just correct the error and log the address).
> > > Obviously a correctible ECC error on a protected memory area (i.e. even the OS
> > > cannot read) would need to panic if the correction is not done in hardware.
> > > Now the question is also, do you only correct the read value (risking un-correctible error
> > > if another bit error appears on that address), or do you write-back the correction?
> > > Next step is not to panic on uncorrectible ECC error, just reload if possible,
> > > or kill only the task affected (or only the virtual machine affected).
> >
> > It all remains unclear.
> > One possibility is that this refers PURELY to ECC in caches (so not especially interesting).
> >
> > Another is that there's the possibility for in-line ECC but this is not yet hooked up?
> >
> > Another is that there is genuine in-line ECC, working exactly as you would
> > hope (and presumably with RAS functionality being added over time, eg even
> > a non-correctable error in a block of memory that also exists on disk).
> >
> > That's all even apart from the issue of how the OS intervenes. Hopefully
> > over the next year or so people will figure out more details.
>
> LPDDR doesn't have ECC, so I am skeptical that Apple uses ECC memory.

It's true that externally LPDDR doesn't have ECC but I've certainly noticed quite a few LPDDR4/LPDDR4x that have on chip ECC, probably in the vein of DDR5. At a guess the LPDDR4s with ECC have the ability to reduce actual memory errors but reading marketing material from Micron they suggest using the added reliability for power savings and thus potentially reducing error robustness to the level of non-ECC memory.

Most of us are probably already aware of the fact that DDR5 will have on chip ECC. Considering the fact that without on chip ECC there is no DDR5, I think the jury is still out on whether this ECC actually helps in reducing the amount of memory errors that reach the CPU.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
In-band ECC support in recent Atom SoCsGabriele Svelto2020/12/15 03:24 PM
  In-band ECC support in recent Atom SoCsanon2020/12/15 05:40 PM
  In-band ECC support in recent Atom SoCsanon32020/12/15 07:07 PM
  In-band ECC support in recent Atom SoCsEtienne Lorrain2020/12/16 01:48 AM
    In-band ECC support in recent Atom SoCsAdrian2020/12/16 07:43 AM
      ECC in SoCsKonrad Schwarz2020/12/17 07:37 AM
        ECC in SoCsAdrian2020/12/17 08:43 AM
          ECC in SoCsMichael S2020/12/17 12:06 PM
  In-band ECC support in recent Atom SoCs & Tiger Lake UAdrian2020/12/16 07:31 AM
    In-band ECC support in recent Atom SoCs & Tiger Lake UJS2020/12/16 09:07 PM
      In-band ECC support in recent Atom SoCs & Tiger Lake UGabriele Svelto2020/12/16 10:00 PM
        In-band ECC support in recent Atom SoCs & Tiger Lake UJS2020/12/17 12:39 AM
          In-band ECC support in recent Atom SoCs & Tiger Lake UEtienne Lorrain2020/12/17 02:15 AM
            In-band ECC support in recent Atom SoCs & Tiger Lake UJames2020/12/17 07:28 AM
              In-band ECC support in recent Atom SoCs & Tiger Lake UEtienne Lorrain2020/12/17 09:16 AM
                In-band ECC support in recent Atom SoCs & Tiger Lake Urwessel2020/12/17 09:51 AM
                  In-band ECC support in recent Atom SoCs & Tiger Lake UMichael S2020/12/17 12:22 PM
    Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/16 10:09 PM
      Enough with the idiocy ... let's have proper ECC again.Maxwell2020/12/17 12:58 AM
        Enough with the idiocy ... let's have proper ECC again.pixiespeed2020/12/17 09:04 AM
      Enough with the idiocy ... let's have proper ECC again.Adrian2020/12/17 07:40 AM
      Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:09 AM
        Enough with the idiocy ... let's have proper ECC again.Etienne Lorrain2020/12/17 09:26 AM
          Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:42 AM
            Enough with the idiocy ... let's have proper ECC again.David Kanter2020/12/17 12:04 PM
              Enough with the idiocy ... let's have proper ECC again.Doug S2020/12/17 01:03 PM
              Enough with the idiocy ... let's have proper ECC again.phonon2020/12/17 03:25 PM
                Internal array ECC vs. memory controllerDavid Kanter2020/12/19 10:39 AM
                  Internal array ECC vs. memory controllerJörn Engel2020/12/20 10:42 AM
                    Internal array ECC vs. memory controllerrwessel2020/12/20 10:52 AM
                    Internal array ECC vs. memory controllerDavid Kanter2020/12/20 03:44 PM
              Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 04:55 PM
                Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/17 07:34 PM
                  Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:10 PM
                    Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:43 PM
                      Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/18 09:30 AM
                        Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 01:00 AM
                          Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/19 10:23 AM
                            Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 03:01 PM
                              Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/19 04:23 PM
                                Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 04:30 PM
              Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/17 07:41 PM
                Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 08:48 PM
              Enough with the idiocy ... let's have proper ECC again.Memory Guy2020/12/17 09:19 PM
      Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/17 10:01 AM
      Enough with the idiocy ... let's have proper ECC again.Wes Felter2020/12/18 09:38 PM
        Thanks for the confirmation!David Kanter2020/12/19 11:51 AM
          Thanks for the confirmation!Konrad Schwarz2020/12/20 09:34 AM
            Thanks for the confirmation!Niels Jørgen Kruse2020/12/20 11:01 AM
              Thanks for the confirmation!David Kanter2020/12/20 03:45 PM
              Thanks for the confirmation!Gionatan Danti2020/12/21 12:50 AM
                Thanks for the confirmation!Niels Jørgen Kruse2020/12/21 09:07 AM
            Thanks for the confirmation!David Kanter2020/12/20 03:42 PM
              Thanks for the confirmation!Foo_2020/12/21 02:01 AM
                Thanks for the confirmation!David Kanter2020/12/21 08:39 AM
            Thanks for the confirmation!Paul2020/12/20 11:29 PM
              Thanks for the confirmation!Michael S2020/12/21 01:00 AM
                Thanks for the confirmation!anon20202020/12/21 01:44 AM
                Thanks for the confirmation!Paul2020/12/22 12:42 PM
                  Thanks for the confirmation!Michael S2020/12/22 02:28 PM
                    Thanks for the confirmation!Paul2020/12/22 06:12 PM
                      Thanks for the confirmation!Michael S2020/12/23 02:55 PM
                        Thanks for the confirmation!Paul2020/12/23 03:54 PM
                          Thanks for the confirmation!Dan Fay2020/12/23 04:38 PM
                            Thanks for the confirmation!Paul2020/12/26 04:10 AM
                              Thanks for the confirmation!Björn Ragnar Björnsson2020/12/26 08:37 PM
                                Thanks for the confirmation!anon22020/12/27 02:00 AM
                                Thanks for the confirmation!Doug S2020/12/28 12:47 PM
            Thanks for the confirmation!David Hess2020/12/21 06:35 PM
              Thanks for the confirmation!Konrad Schwarz2020/12/22 12:08 AM
                Thanks for the confirmation!Doug S2020/12/22 10:42 AM
                  Thanks for the confirmation!David Hess2020/12/22 12:32 PM
                Thanks for the confirmation!David Hess2020/12/22 12:21 PM
        Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 04:25 PM
          Enough with the idiocy ... let's have proper ECC again.Brett2020/12/19 08:13 PM
            Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 09:17 PM
              Enough with the idiocy ... let's have proper ECC again.Konrad Schwarz2020/12/21 03:29 AM
                Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/21 06:49 PM
            Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 09:57 PM
              Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 10:14 PM
            Enough with the idiocy ... let's have proper ECC again.Adrian2020/12/20 02:06 AM
              Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/20 08:43 AM
             Multi-level DRAM?Brett2020/12/20 08:07 PM
               Multi-level DRAM?Heikki Kultala2020/12/21 11:58 AM
               Multi-level DRAM?David Hess2020/12/21 07:25 PM
                 Multi-level DRAM?Adrian2020/12/22 05:15 AM
                   Multi-level DRAM?Dan Fay2020/12/22 10:11 AM
                     Multi-level DRAM?Paul2020/12/22 06:01 PM
                       Multi-level DRAM?Dan Fay2020/12/23 12:29 PM
                         Multi-level DRAM?Paul2020/12/23 01:00 PM
                           Multi-level DRAM?Dan Fay2020/12/23 04:30 PM
                             Multi-level DRAM?David Hess2020/12/23 05:05 PM
                           Multi-level DRAM?Björn Ragnar Björnsson2020/12/25 06:44 PM
                             Multi-level DRAM?Paul2020/12/26 04:04 AM
                               Multi-level DRAM?Michael S2020/12/26 08:11 AM
                                 DIMM binsPaul2020/12/26 08:55 AM
                                   DIMM binsBjörn Ragnar Björnsson2020/12/26 08:09 PM
                                     DIMM binsBjörn Ragnar Björnsson2020/12/26 08:19 PM
                                       DIMM binsDaniel Fay2020/12/27 07:51 PM
                                  Is binning at the module or die level? (NT)anonymous22020/12/27 02:36 PM
                                    Is binning at the module or die level?David Hess2020/12/28 01:31 PM
                               Multi-level DRAM?Doug S2020/12/28 12:55 PM
                               Multi-level DRAM?David Hess2020/12/28 01:36 PM
                             Multi-level DRAM?anon­­32020/12/26 10:22 PM
                               Multi-level DRAM?Björn Ragnar Björnsson2020/12/27 07:12 PM
                               Multi-level DRAM?Paul2021/01/04 04:20 AM
               Multi-level DRAM?Carson2021/01/05 12:14 PM
                 Multi-level DRAM?Brett2021/01/05 02:05 PM
        Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 04:35 PM
        Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 08:59 PM
          Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/20 08:56 AM
          Enough with the idiocy ... let's have proper ECC again.Doug S2020/12/20 10:16 AM
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