phonon (me.delete@this.example.org) on December 17, 2020 3:25 pm wrote:
>
> >
> > LPDDR doesn't have ECC, so I am skeptical that Apple uses ECC memory.
> >
> > I think your interpretation that it's ECC on caches is more likely to be correct.
> >
> > I don't think Apple has the volume to develop non-standard LPDDR memory interfaces
> > and modules. But I could be wrong, and it would be awesome if they did.
> >
> > David
>
> https://media-www.micron.com/-/media/client/global/documents/products/white-paper/ecc_for_mobile_devices_white_paper.pdf
> ?

I'm aware of LPDDR memories using ECC within the array; Samsung published a paper I saw at ISSCC in 2014 that another poster found (as well as this micron whitepaper). However, I believe the purpose of this is not to improve reliability for server-class system operation. It's to enable reducing DRAM array operating voltage into a regime where single-bit errors are low-probability (as opposed to nearly 0 probability), without becoming a reliability problem.

Please feel free to correct if I'm wrong.

But if you look at how ECC is implemented in servers, the bus from memory controller to the memory is wider (e.g., 72b containing 64b of data), and there are more DRAMs as well.

To take the 72b example, you would need 9x8 DRAMs, which is pretty easy for DDR4.


Take the following with a grain of salt. My understanding is that LPDDR5 is typically configured much wider than regular DDR4/5. For example, I believe a lot of LPDDR5 is x32 organizations, which makes the cost of ECC prohibitive. E.g., if you wanted to protect a 128b data bus, you'd need a 160b physical bus.

Can someone tell me what kinds of LPDDR5 are available? Are x4, x8, x16 common?

Better yet - can anyone point me to systems using LPDDR5 with full ECC over the datapath?

David