Thanks for the confirmation!

By: Michael S (already5chosen.delete@this.yahoo.com), December 23, 2020 2:55 pm
Room: Moderated Discussions
Paul (pavel.delete@this.noa-labs.com) on December 22, 2020 6:12 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on December 22, 2020 2:28 pm wrote:
> > Paul (pavel.delete@this.noa-labs.com) on December 22, 2020 12:42 pm wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on December 21, 2020 1:00 am wrote:
> > > > Paul (pavel.delete@this.noa-labs.com) on December 20, 2020 11:29 pm wrote:
> > > > > Konrad Schwarz (no.spam.delete@this.no.spam) on December 20, 2020 9:34 am wrote:
> > > > > > David Kanter (dkanter.delete@this.realworldtech.com) on December 19, 2020 11:51 am wrote:
> > > > > > > As I've said before, the ECC that is being done in LPDDR is entirely different from ECC for server memory.
> > > > > >
> > > > > > Why can't servers profit from ECC integrated into DRAM?
> > > > > >
> > > > > > If ECC detection and correction can be done by the memory
> > > > > > device autonomously during row refresh cycles would
> > > > > > seem to be a big win, except that you need x64 devices. The
> > > > > > fact that correctable errors will no longer be reported
> > > > > > precisely seems like a secondary concern; simple parity could be used to ensure correct transfers.
> > > > > >
> > > > >
> > > > > This is where the embedded seems to be going to
> > > > >
> > > > > http://www.xingmem.com/en/product_xm8a.php
> > > > >
> > > > > If you can make devices use ECC to hide the refresh cycle, and all the DRAM peculiarities, you
> > > > > get a dumb SRAM like interface facing the system, greatly simplifying the host SoC/MCU design.
> > > >
> > > >
> > > > You can't hide variable latency of access except by make best-case latency huge.
> > > >
> > >
> > > You can!
> > >
> > > You just don't use the data written/read from the row being refreshed, and use
> > > multi-bit error correction codes to "hide" that. This is how that XRAM works.
> > >
> > > You just need to make sure that the smallest accessible piece
> > > of RAM covers more real rows than error correction
> > > can fix, and do error correction on read to cover the case when read comes instantly after write.
> >
> > Even ignoring refresh, today in many workloads more than half of accesses are Row Hits which are 2 times
> > faster* than Raw Misses (i.e. accesses to fully precharged bank) and 3 times faster than Raw Conflicts
> > (i.e. accesses to bank that is currently active with different raw). In fixed-latency setup you will have
> > all accesses as slow as Raw Conflicts which would be more than twice slower than today's average.
> > And that's before we consider limitations imposed by limited supply current, in particular tFAW. Or,
> > may be, maximal sustained bandwidth of this devices is so low that tFAW never becomes an issue?
> >
> > ---------------
> > * - All latencies, as measured on memory device balls
> >
>
> 166mhz with 4ns Tco. Completely nothing to sneeze at.
>


Almost 40 times lower bandwidth than state of the art DDR5 is also not something to be particularly proud of. However it *is* quick enough for current limiters off-the-shelf DRAM devices like tFAV and even more importantly tRRD to become a problem. Of course, if they design an array by themselves, they are free to use much smaller pages (rows) than off-the-shelf parts. That will allow shorter tRRD and could completely eliminate tFAV.

BTW, what series are your talking about? Supposedly, XM7A? But I can't find a datasheet for this series. Without a datasheet, I can only guess what tCO actually means and if it applies to CL=1 or CL=2. Also, in order to calculate practically achievable latency for synchronous device we should know few other numbers apart from tCO and CL, most importantly, tSU/tH of address/control lines.

XM8A in at your link appear to be 100 MHz in theory, but, accounting for various board and buffering delay a real-world design would get trouble beating 65-70 MT/s.

> I believe you can avoid hitting a conflict if you always spread bits on more banks than your
> data width. And you can tweak your error correction so that it will always be able to provide
> more correction than maximum possible number of rows being precharged at given frequency.

Overall, call me skeptical. IMHO, they are going nowhere.
Ancient PC133 SDR SDRAM sounds like better proposition than either XM8A or XM7A and controller for it is not complicated at all.
As to XM6A, how exactly am I going to connect it to MCU or to old cheap FPGA that lacks dedicated DDR3 phy? And if I have newer/less cheap part, one with DDR3 phy, then it probably has DDR3 DRAM controller as well or, if it is FPGA, controller can be implemented with relative ease.

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TopicPosted ByDate
In-band ECC support in recent Atom SoCsGabriele Svelto2020/12/15 03:24 PM
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  In-band ECC support in recent Atom SoCsEtienne Lorrain2020/12/16 01:48 AM
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      ECC in SoCsKonrad Schwarz2020/12/17 07:37 AM
        ECC in SoCsAdrian2020/12/17 08:43 AM
          ECC in SoCsMichael S2020/12/17 12:06 PM
  In-band ECC support in recent Atom SoCs & Tiger Lake UAdrian2020/12/16 07:31 AM
    In-band ECC support in recent Atom SoCs & Tiger Lake UJS2020/12/16 09:07 PM
      In-band ECC support in recent Atom SoCs & Tiger Lake UGabriele Svelto2020/12/16 10:00 PM
        In-band ECC support in recent Atom SoCs & Tiger Lake UJS2020/12/17 12:39 AM
          In-band ECC support in recent Atom SoCs & Tiger Lake UEtienne Lorrain2020/12/17 02:15 AM
            In-band ECC support in recent Atom SoCs & Tiger Lake UJames2020/12/17 07:28 AM
              In-band ECC support in recent Atom SoCs & Tiger Lake UEtienne Lorrain2020/12/17 09:16 AM
                In-band ECC support in recent Atom SoCs & Tiger Lake Urwessel2020/12/17 09:51 AM
                  In-band ECC support in recent Atom SoCs & Tiger Lake UMichael S2020/12/17 12:22 PM
    Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/16 10:09 PM
      Enough with the idiocy ... let's have proper ECC again.Maxwell2020/12/17 12:58 AM
        Enough with the idiocy ... let's have proper ECC again.pixiespeed2020/12/17 09:04 AM
      Enough with the idiocy ... let's have proper ECC again.Adrian2020/12/17 07:40 AM
      Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:09 AM
        Enough with the idiocy ... let's have proper ECC again.Etienne Lorrain2020/12/17 09:26 AM
          Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:42 AM
            Enough with the idiocy ... let's have proper ECC again.David Kanter2020/12/17 12:04 PM
              Enough with the idiocy ... let's have proper ECC again.Doug S2020/12/17 01:03 PM
              Enough with the idiocy ... let's have proper ECC again.phonon2020/12/17 03:25 PM
                Internal array ECC vs. memory controllerDavid Kanter2020/12/19 10:39 AM
                  Internal array ECC vs. memory controllerJörn Engel2020/12/20 10:42 AM
                    Internal array ECC vs. memory controllerrwessel2020/12/20 10:52 AM
                    Internal array ECC vs. memory controllerDavid Kanter2020/12/20 03:44 PM
              Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 04:55 PM
                Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/17 07:34 PM
                  Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:10 PM
                    Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/17 09:43 PM
                      Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/18 09:30 AM
                        Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 01:00 AM
                          Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/19 10:23 AM
                            Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 03:01 PM
                              Enough with the idiocy ... let's have proper ECC again.Maynard Handley2020/12/19 04:23 PM
                                Enough with the idiocy ... let's have proper ECC again.anon22020/12/19 04:30 PM
              Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/17 07:41 PM
                Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 08:48 PM
              Enough with the idiocy ... let's have proper ECC again.Memory Guy2020/12/17 09:19 PM
      Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/17 10:01 AM
      Enough with the idiocy ... let's have proper ECC again.Wes Felter2020/12/18 09:38 PM
        Thanks for the confirmation!David Kanter2020/12/19 11:51 AM
          Thanks for the confirmation!Konrad Schwarz2020/12/20 09:34 AM
            Thanks for the confirmation!Niels Jørgen Kruse2020/12/20 11:01 AM
              Thanks for the confirmation!David Kanter2020/12/20 03:45 PM
              Thanks for the confirmation!Gionatan Danti2020/12/21 12:50 AM
                Thanks for the confirmation!Niels Jørgen Kruse2020/12/21 09:07 AM
            Thanks for the confirmation!David Kanter2020/12/20 03:42 PM
              Thanks for the confirmation!Foo_2020/12/21 02:01 AM
                Thanks for the confirmation!David Kanter2020/12/21 08:39 AM
            Thanks for the confirmation!Paul2020/12/20 11:29 PM
              Thanks for the confirmation!Michael S2020/12/21 01:00 AM
                Thanks for the confirmation!anon20202020/12/21 01:44 AM
                Thanks for the confirmation!Paul2020/12/22 12:42 PM
                  Thanks for the confirmation!Michael S2020/12/22 02:28 PM
                    Thanks for the confirmation!Paul2020/12/22 06:12 PM
                      Thanks for the confirmation!Michael S2020/12/23 02:55 PM
                        Thanks for the confirmation!Paul2020/12/23 03:54 PM
                          Thanks for the confirmation!Dan Fay2020/12/23 04:38 PM
                            Thanks for the confirmation!Paul2020/12/26 04:10 AM
                              Thanks for the confirmation!Björn Ragnar Björnsson2020/12/26 08:37 PM
                                Thanks for the confirmation!anon22020/12/27 02:00 AM
                                Thanks for the confirmation!Doug S2020/12/28 12:47 PM
            Thanks for the confirmation!David Hess2020/12/21 06:35 PM
              Thanks for the confirmation!Konrad Schwarz2020/12/22 12:08 AM
                Thanks for the confirmation!Doug S2020/12/22 10:42 AM
                  Thanks for the confirmation!David Hess2020/12/22 12:32 PM
                Thanks for the confirmation!David Hess2020/12/22 12:21 PM
        Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 04:25 PM
          Enough with the idiocy ... let's have proper ECC again.Brett2020/12/19 08:13 PM
            Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 09:17 PM
              Enough with the idiocy ... let's have proper ECC again.Konrad Schwarz2020/12/21 03:29 AM
                Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/21 06:49 PM
            Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 09:57 PM
              Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 10:14 PM
            Enough with the idiocy ... let's have proper ECC again.Adrian2020/12/20 02:06 AM
              Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/20 08:43 AM
             Multi-level DRAM?Brett2020/12/20 08:07 PM
               Multi-level DRAM?Heikki Kultala2020/12/21 11:58 AM
               Multi-level DRAM?David Hess2020/12/21 07:25 PM
                 Multi-level DRAM?Adrian2020/12/22 05:15 AM
                   Multi-level DRAM?Dan Fay2020/12/22 10:11 AM
                     Multi-level DRAM?Paul2020/12/22 06:01 PM
                       Multi-level DRAM?Dan Fay2020/12/23 12:29 PM
                         Multi-level DRAM?Paul2020/12/23 01:00 PM
                           Multi-level DRAM?Dan Fay2020/12/23 04:30 PM
                             Multi-level DRAM?David Hess2020/12/23 05:05 PM
                           Multi-level DRAM?Björn Ragnar Björnsson2020/12/25 06:44 PM
                             Multi-level DRAM?Paul2020/12/26 04:04 AM
                               Multi-level DRAM?Michael S2020/12/26 08:11 AM
                                 DIMM binsPaul2020/12/26 08:55 AM
                                   DIMM binsBjörn Ragnar Björnsson2020/12/26 08:09 PM
                                     DIMM binsBjörn Ragnar Björnsson2020/12/26 08:19 PM
                                       DIMM binsDaniel Fay2020/12/27 07:51 PM
                                  Is binning at the module or die level? (NT)anonymous22020/12/27 02:36 PM
                                    Is binning at the module or die level?David Hess2020/12/28 01:31 PM
                               Multi-level DRAM?Doug S2020/12/28 12:55 PM
                               Multi-level DRAM?David Hess2020/12/28 01:36 PM
                             Multi-level DRAM?anon­­32020/12/26 10:22 PM
                               Multi-level DRAM?Björn Ragnar Björnsson2020/12/27 07:12 PM
                               Multi-level DRAM?Paul2021/01/04 04:20 AM
               Multi-level DRAM?Carson2021/01/05 12:14 PM
                 Multi-level DRAM?Brett2021/01/05 02:05 PM
        Enough with the idiocy ... let's have proper ECC again.Björn Ragnar Björnsson2020/12/19 04:35 PM
        Enough with the idiocy ... let's have proper ECC again.David Hess2020/12/19 08:59 PM
          Enough with the idiocy ... let's have proper ECC again.rwessel2020/12/20 08:56 AM
          Enough with the idiocy ... let's have proper ECC again.Doug S2020/12/20 10:16 AM
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