By: Jörn Engel (joern.delete@this.purestorage.com), January 7, 2021 5:29 pm
Room: Moderated Discussions
rwessel (rwessel.delete@this.yahoo.com) on January 7, 2021 9:25 am wrote:
>
> So SECDEC on a 32-bit word requires seven bits, eight bits on a 64-bit word, nine bits on a 128-bit word.
> Doing that on 64-bit words has the advantage of allowing fairly simple 8x9 or 9x8 RAM configurations.
If the memory interface is 64bit, but the cacheline size is 64 _Bytes_, you need to do 8 reads anyway. I wonder how hard it would be to do 9 reads to get the extra ECC information. That would simplify things quite a bit, you can use the same DIMMs and motherboards. You can also get away with relatively fewer bits for ECC, so it might be possible to reduce overhead from 12.5% to something closer to 2.15%. Memory bandwidth is reduced by 11%, which would be fine in my book.
Any CPU manufacturer should be able to do something like that. And I believe I can find old implementations of that going back close to 20 years. So why isn't it done all the time?
>
> So SECDEC on a 32-bit word requires seven bits, eight bits on a 64-bit word, nine bits on a 128-bit word.
> Doing that on 64-bit words has the advantage of allowing fairly simple 8x9 or 9x8 RAM configurations.
If the memory interface is 64bit, but the cacheline size is 64 _Bytes_, you need to do 8 reads anyway. I wonder how hard it would be to do 9 reads to get the extra ECC information. That would simplify things quite a bit, you can use the same DIMMs and motherboards. You can also get away with relatively fewer bits for ECC, so it might be possible to reduce overhead from 12.5% to something closer to 2.15%. Memory bandwidth is reduced by 11%, which would be fine in my book.
Any CPU manufacturer should be able to do something like that. And I believe I can find old implementations of that going back close to 20 years. So why isn't it done all the time?