Michael S (already5chosen.delete@this.yahoo.com) on January 8, 2021 2:31 am wrote:
> Chester (lamchester.delete@this.gmail.com) on January 7, 2021 4:19 pm wrote:
> >
> > I'm not arguing against airbags because they won't stop a stray meteorite. I'm arguing against
> > driving at 100 MPH because airbags will (maybe) save you. Notice people didn't create bit flips
> > in L1D (also ECC protected), even though that's a lot easier to hammer than ECC DRAM. L1D is designed
> > to handle very frequent accesses to the same rows. DRAM is not, because of caches.
> >
>
> Off topic.
> According to my understanding
> - nearly all L1I caches you ares likely to encounter are not ECC protected.
> - L1D in big Intel cores is not ECC protected since Nehalem
> - L1D in IBM CPUs (Z, POWER) never was ECC-protected, but then again, IBM uses WT L1Ds, so parity suffice
>
> I don't know what others (AMD, Intel's Atom series, various ARM vendors) are doing in that regard. As
> to ARM-designed cores, L1D ECC appears to be optional in client cores, but mandatory in server cores.
>

Most L1I were protected with parity, unlike L1D which were protected with ECC.

It is true that looking right now in the datasheet of Cascade Lake, I could no longer see any information about how the caches are protected.

Nevertheless, it is hard for me to believe that they have stopped using any kind of EDC/ECC in L1, like they were using in the past.

It seems more likely that they are no longer documenting what they are using.