By: David Kanter (dkanter.delete@this.realworldtech.com), January 8, 2021 9:13 am
Room: Moderated Discussions
> Most L1I were protected with parity, unlike L1D which were protected with ECC.
>
> It is true that looking right now in the datasheet of Cascade Lake, I could
> no longer see any information about how the caches are protected.
>
> Nevertheless, it is hard for me to believe that they have stopped using
> any kind of EDC/ECC in L1, like they were using in the past.
>
> It seems more likely that they are no longer documenting what they are using.
They don't have ECC on L1. The cache is implemented in RF cells (so 8T bit cells), which are much less susceptible to bit flips because they store more charge and isolate R/W. Additionally, FinFETs dramatically reduce the susceptibility to SERs.
David
>
> It is true that looking right now in the datasheet of Cascade Lake, I could
> no longer see any information about how the caches are protected.
>
> Nevertheless, it is hard for me to believe that they have stopped using
> any kind of EDC/ECC in L1, like they were using in the past.
>
> It seems more likely that they are no longer documenting what they are using.
They don't have ECC on L1. The cache is implemented in RF cells (so 8T bit cells), which are much less susceptible to bit flips because they store more charge and isolate R/W. Additionally, FinFETs dramatically reduce the susceptibility to SERs.
David
