By: rwessel (rwessel.delete@this.yahoo.com), January 19, 2021 5:45 pm
Room: Moderated Discussions
It's hard to believe it's been a quarter century since the first announcements of what would become Itanium, and almost 20 years since the first shipments of Merced (July 2001), but it has.
This past December 31st was the last day HPE would accept orders for Itanium hardware, a few days from now (January 30th) is Intel's official last order date (last shipment date is July 29th, assuming they have any open orders).
Obviously that turned out to be a disaster on all fronts, any hopes for the architecture spoiled by poor performance, terrible execution, poor compatibility, fast advances in x86 land, and impossible demands on compilers.
At least we have to give some credit to Intel (and HP) for trying something different. These days "interesting" discussions about ISAs revolve around such earth-shaking fundamentals as to which ISA has better constant load instructions, or over whose mostly worthless vector extension is slightly less worthless. Bah, humbug.
As they say, "It's dead, Jim".
This past December 31st was the last day HPE would accept orders for Itanium hardware, a few days from now (January 30th) is Intel's official last order date (last shipment date is July 29th, assuming they have any open orders).
Obviously that turned out to be a disaster on all fronts, any hopes for the architecture spoiled by poor performance, terrible execution, poor compatibility, fast advances in x86 land, and impossible demands on compilers.
At least we have to give some credit to Intel (and HP) for trying something different. These days "interesting" discussions about ISAs revolve around such earth-shaking fundamentals as to which ISA has better constant load instructions, or over whose mostly worthless vector extension is slightly less worthless. Bah, humbug.
As they say, "It's dead, Jim".
