By: Brett (ggtgp.delete@this.yahoo.com), February 21, 2021 11:59 pm
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on February 21, 2021 10:25 pm wrote:
> Moritz (better.delete@this.not.tell) on February 20, 2021 9:45 am wrote:
> > 12:30 "[ISA] do not matter very much"
>
> First Andy Glew and now Jim Keller?! In light of this new information,
> my worldview needs revising: clearly these guys are morons.
>
> Is there truly not one reputable twitter-based CPU design expert who can
> see it upon themselves to comfort me and set these two hacks straight?!?
A crap ISA like x86 will cost you a few extra stages of decode and thus a longer pipe which will net a few percent slower. Does not matter very much. Historically Intel’s fab advantage and cubic dollars design advantage dwarfed this minor disadvantage.
There is the example of the Power designs which switched from one of the most complex long pipelines to a simple pipeline with not a lot of net difference.
The RISC religion of only 2 inputs and one output is crushed by the advantage of complex addressing modes with 3 or more sources, never mind Multiply accumulate with 3 or 4 sources.
I am a big fan of the Mill approach as it exposes chains of operations making opcode merging easier and does so in way that decreases opcode size. You get a potential critical operation chain length reduction which can get you 10% in some cases and the smaller opcodes get you another few percent. This is why I promoted a OoOe version of Mill that is slightly different, which is against the world view of the Mill founders. The in-order wide advantage of the Mill team is a loser against OoOe running typical low IPC code.
> Moritz (better.delete@this.not.tell) on February 20, 2021 9:45 am wrote:
> > 12:30 "[ISA] do not matter very much"
>
> First Andy Glew and now Jim Keller?! In light of this new information,
> my worldview needs revising: clearly these guys are morons.
>
> Is there truly not one reputable twitter-based CPU design expert who can
> see it upon themselves to comfort me and set these two hacks straight?!?
A crap ISA like x86 will cost you a few extra stages of decode and thus a longer pipe which will net a few percent slower. Does not matter very much. Historically Intel’s fab advantage and cubic dollars design advantage dwarfed this minor disadvantage.
There is the example of the Power designs which switched from one of the most complex long pipelines to a simple pipeline with not a lot of net difference.
The RISC religion of only 2 inputs and one output is crushed by the advantage of complex addressing modes with 3 or more sources, never mind Multiply accumulate with 3 or 4 sources.
I am a big fan of the Mill approach as it exposes chains of operations making opcode merging easier and does so in way that decreases opcode size. You get a potential critical operation chain length reduction which can get you 10% in some cases and the smaller opcodes get you another few percent. This is why I promoted a OoOe version of Mill that is slightly different, which is against the world view of the Mill founders. The in-order wide advantage of the Mill team is a loser against OoOe running typical low IPC code.
