Andrey (andrey.semashev.delete@this.gmail.com) on February 25, 2021 1:34 pm wrote:
> Linus Torvalds (torvalds.delete@this.linux-foundation.org) on February 25, 2021 10:35 am wrote:
> > ...
> > Google "A tale of an impossible bug".
>
> An interesting tale indeed. It doesn't invalidate my point though. I mean, cache line size is naturally
> CPU-specific, and different cache line sizes on different kinds of cores are clearly possible (though
> I'm not convinced that it's sane). Cache manipulation instructions are naturally aligned to the cache
> line size, nothing unreasonable there. The problem here is not the instructions, its the historical software
> expectations of the hardware that no longer hold true. We can argue whether heterogeneous CPU cores is
> a good thing or not, but it is not really relevant to ISAs and instruction definitions.
>

I seem to remember that some PCIe video card advertise cache-line size of 128 bytes (on x86 system where the processor has 64 bytes). That may complexify things a bit, cache line size depending on addresses, different cache line size from source to destination...