Doug S (foo.delete@this.bar.bar) on March 4, 2021 10:48 am wrote:
> Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on March 4, 2021 6:26 am wrote:
> > dmcq (dmcq.delete@this.fano.co.uk) on March 4, 2021 5:16 am wrote:
> > > ...
> > >
> > > I think the important thing is error detection - not recovery. Error recovery at a low level is nice to
> > > have but if the whole business can be fixed at a higher level and the error rate is low enough it is not
> > > really necessary. Intel leaving out ECC was dreadful, the
> > > thing that I think was really criminal and cretinous
> > > though was cutting out even parity checking. I see it as a cheap trick to obscure errors so people just
> > > blamed gremlins and pressed ctrl-alt-delete rather than fixing underlyng problems. Of course some memory
> > > problems would escape that but it would catch memory that is failing and it would give an indication of
> > > how reliable it is overall.
> >
> > Historically, I think ECC error detection was removed approximately at the time it took too much time to
> > initialise the memory. At power-up, the parity bit is not
> > initialised: if you dump the DDR before initialisation
> > you get mostly zero bits but you will also get bits set (I do not know why the capacitor is still charged
> > at power-up). If you do a quick power-cycle, it is obvious you will still have bits set.
> > When the memory of the PC increased to few tens of megabytes, the CPU (at that time) was
> > not able to clear that DRAM (so initialise the ECC) in less than 10 seconds, and the PC never
> > had a powerful DMA to do such work. To cut boot time, they removed the parity bit.
>
>
> That would have been easy enough to fix in the next generation of memory (i.e. when they went
> from FBDIMM to SDRAM or whatever) by adding a reset pin that would be triggered on power on
> that would cause the entire chip to be zeroed without the CPU having to take part. All the
> chips could do it in parallel, so whatever the worst case time (which could be defined in the
> standard as a requirement) was would apply regardless of how much memory was installed.

It's not that simple.
There are trade offs between speed of zeroing and consumed current that are quite different in system vs 2 memory ranks vs one with, for example, 16 ranks.
Individual memory chip do not see a whole picture so has no chance to make an optimal decision.
Host-controlled "zeroize row" command looks like better idea.
Isn't something like that already available GDDR SDRAM?