By: Moritz (better.delete@this.not.tell), March 21, 2021 9:45 am
Room: Moderated Discussions
I read/understood so far:
# Architecture independent intermediate representation that frees the HW from removing legacy HW specific constructs
# Less implicit constrains by using HLL that is about WHAT but not HOW.
# Explicit "I do not care about ..." annotations for when the language does not allow otherwise
# The architecture must not force the program to specify operations that do not generate output-results. These might be control flow or resource use related
# Microthreading by short sequential blocks of instructions with delimiter
# Low latency and granularity offloading to configurable long and wide data path from the last level cache.
I was talking about a general purpose architecture that is not just like some historic non Intel architecture and that is not as parallel and restricted as a GPU. I was not talking about highly speculative execution to process inherently serial code either. I was not talking about an architecture compatible with existing low level source code. If there is no inner thread parallelism near nor far, then one can still make the processor more energy efficient.
How would an engineer with zero knowledge of the past, but four billion transistors at his/her disposal do it today?
Such a person would not even know the concept of a single core single thread RISC von-Neumann-architecture.
Why even feed a single type of instruction stream / thread into the CPU? The compiler could discompose the program into a front-end+back-end part that interfaces with the 64 bit memory and execution resources and a part that configures the execution resources to process the data that it gets fed by the first part. Many tasks/functions that are handled in hardware today have to guess what is going on could be made explicit. The inner (EU) part of the CPU would not have to compute 64 bit addresses if it did not have to know/handle where the data is coming from and going to. On die caching could be handled explicitly in a 32 bit address space.
# Architecture independent intermediate representation that frees the HW from removing legacy HW specific constructs
# Less implicit constrains by using HLL that is about WHAT but not HOW.
# Explicit "I do not care about ..." annotations for when the language does not allow otherwise
# The architecture must not force the program to specify operations that do not generate output-results. These might be control flow or resource use related
# Microthreading by short sequential blocks of instructions with delimiter
# Low latency and granularity offloading to configurable long and wide data path from the last level cache.
I was talking about a general purpose architecture that is not just like some historic non Intel architecture and that is not as parallel and restricted as a GPU. I was not talking about highly speculative execution to process inherently serial code either. I was not talking about an architecture compatible with existing low level source code. If there is no inner thread parallelism near nor far, then one can still make the processor more energy efficient.
How would an engineer with zero knowledge of the past, but four billion transistors at his/her disposal do it today?
Such a person would not even know the concept of a single core single thread RISC von-Neumann-architecture.
Why even feed a single type of instruction stream / thread into the CPU? The compiler could discompose the program into a front-end+back-end part that interfaces with the 64 bit memory and execution resources and a part that configures the execution resources to process the data that it gets fed by the first part. Many tasks/functions that are handled in hardware today have to guess what is going on could be made explicit. The inner (EU) part of the CPU would not have to compute 64 bit addresses if it did not have to know/handle where the data is coming from and going to. On die caching could be handled explicitly in a 32 bit address space.
