I'd like to be able to NOT specify order for some things ...

By: Victor Alander (Victor.alander.delete@this.gmail.com), March 21, 2021 5:14 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on March 21, 2021 9:47 am wrote:
> I wasn't clear.
>
> I don't want the ability to run threads/tasks in parallel added to the ISA/IR. I know how to do that :-)
>
> I want the ability to run zero-overhead independent threads in parallel added to the ISA. Think
> of something more like CUDA/GPU blocks. Each block is supposed to be independent and the underlying
> hardware is permitted to run as many blocks in parallel as it has resources for. In the limit (though
> I don't think this has ever happened) the blocks would run sequentially. More expensive GPUs can
> run over 100 blocks in parallel. The overhead to launch these is small (zero?).
>
> The problem with OS threads/tasks is that they are so heavyweight that many
> cases where you COULD logically parallelize code (or, really, just NOT serialize
> it) aren't worth doing because the overhead kills all the gains.
>
> There is a chicken-and-egg p problem here, of course.
> *) The languages need to support this, and
> *) The hardware needs to support this too (or no one will use the feature)
>
> For lots of code I see this would be quite nice. But I suspect my code may be pretty
> niche and I don't know how often this would be useful in more general purpose code.

I have been toying with the idea of a maximally parallel instruction set. The idea is that each instruction has a buffer for it's parameters and a count for how many bytes remain to be written before the instruction has all its inputs so that it can run. When a instruction finishes it has a list of relative addresses to copy all it's output parameters to and each time it copies a byte it decrements the receiving instructions parameters_remaining count by one. A instruction is queued to run in it's relevant function unit when it's parameters_remaining count reaches zero.


(size), parameters_remaining, instruction, [parameters], [[copy output 1 to +100, +29],[copy output 2 to nowhere],...,[copy output n to +256]]


size could be inferred from the instruction but it might be good to have it in the asm for fast look ahead.

parameters_remaining is a atomic count of how many bytes remain to be written to the buffer. It can be lower than the number of inputs a instruction has if some inputs are constants.

instruction has the same size as a pointer and may be the memory mapped location of a function unit or the entry point of a function block implementing the same functionality in code. The instruction may be replaced with a implementation specific pointer when the program is loaded(the ISA is like Unicode where local representations may map the code points however they wish).

[parameters] is a fixed size array for a instructions input and output parameters. It may only be written twice, once when parameters are set by preceding instructions and a second time when the array is overwritten by a copy from the returning function unit.

[[outputs]] is a fixed size compile time constant 2d-array specifying relative copies for each byte of the output parameters, each byte may be sent to multiple destinations. It may not be modified during execution. That each move is to a valid location in a instruction's parameter list in the same function unit can be verified at load.(parameters_remaining can be verified at the same time so that there is always as many writes to [parameters] as parameters_remaining specifies.

When a function block is entered a memory block is allocated for it and it's instructions are copied over in full or only constant parameters(with a reference back to the code). The first case is preferred for code locality while the second offer better security by separating instructions and data. The function block is deallocated (or reused if it is recursive) when it's return statement's parameters_remaining reaches zero.

Function calls/instructions and returns/jumps are the only parts that ever handle absolute pointers to asm. Code may handle pointers to data.

My attempt at writing a ToUpper function in a hypothetical ISA, format is:
instruction(inputs)(outputs)
outputs can take over variable names or be discarded in to the void.


@readLine func , , , ;
readStream [readLine:3]; //returns ,
append [readLine:4], [readLine+1:1]; //returns ,
sub [readLine:1], [readLine+1:1]; //returns ,
ifElseZero [readLine], [readLine:0], [readLine+3:1], // select first or second function to jump to depending on third parameter being zero
[readLine:1], [readLine+1:0], [readLine+2:0]; // return is identical to function declaration

func readLine( delimiter, cin, buffer){
readStream(cin, void)(cin, char);
append(buffer, char)(buffer, void);
sub(delimiter, char)(void, comp);
returnOnZero(comp, delimiter, cin, buffer);//or returnOnZero(comp);
}

func writeBuffer( cout, <iterator<> pos, <iterator<> end){
<iterator<> pos(buffer.begin), end(buffer.end)
readIterator(pos, void)(void, char);
incrementIterator(pos)(pos);
writeStream(cout, char)(cout, void);
sub(pos, end)(void, comp);
returnOnZero(comp, cout, pos, end);
}

func toUpper( cin, cout){
buffer();
delimiter(10), diff(32), lower('a'), upper('z');
readLine(delimiter, cin, buffer)(delimiter, cin, buffer);
apply(buffer, x >= lower && x <= upper ? x - diff : x)(buffer);//how to implement SIMD?
<iterator<> pos(buffer.begin), end(buffer.end);
writeBuffer(cout, pos, end)(cout, pos, end);
return(cin, cout);
}


The file format would include a table with the location of all function unit entry points(and also instructions) allowing for embarrassingly parallel program load.

Self modifying code is not allowed except for the modification of jump locations restricted to a predefined list of allowed destinations(function unit entry points). The program is never given actual jump addresses only indexes/keys.

Possible embarrassingly parallel OOO security measures may include:


func jump_check(dest, parameters, definition){
if(!set_of_all_entery_points.in_set(dest) || parameters != definition){die();}
}

func instruction_check(instruction){
if(!set_of_all_loaded_instructions.in_set(&instruction << sizeof(instruction) | instruction)){die();}
}


That will hopefully stop all code injection and unaligned jump attacks.
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TopicPosted ByDate
What are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 05:21 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Stanislav Shwartsman2021/03/20 06:22 AM
    I like the analysis of current arch presentedMoritz2021/03/20 10:13 AM
    Did you read this old article?Michael S2021/03/21 02:12 AM
  Deliver programs in IRHugo Décharnes2021/03/20 07:34 AM
    Java bytecode and Wasm exist, why invent something else? (NT)Foo_2021/03/20 08:01 AM
      Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 08:55 AM
        Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 10:50 AM
          Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 12:40 PM
            Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 04:54 PM
              It's called source code, no?anonymou52021/03/21 12:43 AM
                It's called source code, no?Foo_2021/03/21 05:07 AM
                Thoughts on software distribution formatsPaul A. Clayton2021/03/22 01:45 PM
    Deliver programs in IRJames2021/03/20 11:24 AM
      Deliver programs in IRHugo Décharnes2021/03/20 12:28 PM
        Deliver programs in IRHugo Décharnes2021/03/20 12:36 PM
    Deliver programs in IRLinus Torvalds2021/03/20 01:20 PM
      Deliver programs in IRHugo Décharnes2021/03/20 01:51 PM
      I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/20 05:49 PM
        I'd like to be able to NOT specify order for some things ...Jukka Larja2021/03/21 12:26 AM
          NOT (unintentionally) specify orderMoritz2021/03/21 06:00 AM
            NOT (unintentionally) specify orderJukka Larja2021/03/22 07:11 AM
              NOT (unintentionally) specify orderMoritz2021/03/22 12:40 PM
                NOT (unintentionally) specify orderJukka Larja2021/03/23 06:26 AM
          I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/21 09:47 AM
            I'd like to be able to NOT specify order for some things ...Victor Alander2021/03/21 05:14 PM
      Next architecture will start with MLwumpus2021/03/21 12:24 PM
        Next architecture will start with MLLinus Torvalds2021/03/21 02:38 PM
          Maybe SQL was the better example for general purpose machineswumpus2021/03/22 08:33 AM
            Maybe SQL was the better example for general purpose machinesanon2021/03/22 09:10 AM
        Next architecture will start with MLML will move to PIM2021/03/22 03:51 AM
    Deliver programs in IRanon2021/03/21 03:22 AM
      Deliver programs in IRanon22021/03/21 04:52 AM
        Deliver programs in IRrwessel2021/03/21 05:05 AM
          Deliver programs in IRanon22021/03/21 07:08 PM
            Deliver programs in IRrwessel2021/03/21 10:47 PM
              Deliver programs in IRdmcq2021/03/22 04:33 AM
                Deliver programs in IRrwessel2021/03/22 06:27 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Veedrac2021/03/20 11:27 AM
    Cray MTAanon2021/03/20 06:04 PM
      Cray MTAChester2021/03/20 07:54 PM
        Cray MTAVeedrac2021/03/21 01:33 AM
          Cray MTAnoone2021/03/21 09:15 AM
            Cray MTAVeedrac2021/03/21 10:54 AM
    monolithic 3Dwumpus2021/03/21 12:50 PM
  What are your ideas for a radically different CPU ISA + physical Arch?Anon2021/03/21 12:06 AM
  What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 05:02 AM
  What are your ideas for a radically different CPU ISA + physical Arch?juanrga2021/03/21 05:46 AM
  Summery so farMoritz2021/03/21 09:45 AM
    Summery so farrwessel2021/03/21 11:23 AM
      not staticMoritz2021/03/26 10:12 AM
        Dynamic meta instruction encoding for instruction window compressionMoritz2021/03/28 03:28 AM
          redistributing the work between static compiler, dynamic compiler, CPUMoritz2021/04/05 03:21 AM
            redistributing the work between static compiler, dynamic compiler, CPUdmcq2021/04/05 09:27 AM
    Summery so farAnon2021/03/21 08:53 PM
  What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 10:10 AM
    What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 11:26 AM
      What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 11:34 AM
        What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 12:55 PM
          What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 01:31 PM
      What are your ideas for a radically different CPU ISA + physical Arch?gallier22021/03/22 12:49 AM
  What are your ideas for a radically different CPU ISA + physical Arch?dmcq2021/03/21 03:50 PM
  Microthread/low IPCEtienne Lorrain2021/03/22 03:22 AM
    Microthread/low IPCdmcq2021/03/22 04:24 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 06:10 AM
        Microthread/low IPCdmcq2021/03/22 08:24 AM
    Microthread/low IPCdmcq2021/03/22 04:53 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 05:46 AM
      Microthread/low IPCAnon2021/03/22 05:47 AM
    Microthread/low IPCHeikki Kultala2021/03/22 05:47 PM
      Microthread/low IPCEtienne Lorrain2021/03/23 03:36 AM
        Microthread/low IPCNyan2021/03/24 03:00 AM
          Microthread/low IPCEtienne Lorrain2021/03/24 04:23 AM
      Microthread/low IPCAnon2021/03/23 08:16 AM
        Microthread/low IPCgai2021/03/23 09:37 AM
          Microthread/low IPCAnon2021/03/23 10:17 AM
            Microthread/low IPCdmcq2021/03/23 12:42 PM
  Have you looked at "The Mill CPU" project? (nt)Anon C2021/03/22 06:21 AM
    Have you looked at "The Mill CPU" project? (nt)Moritz2021/03/22 12:13 PM
      Have you looked at "The Mill CPU" project? (nt)Andrew Clough2021/03/22 04:27 PM
        The Mill = vaporwareRichardC2021/03/23 12:47 PM
          The Mill = vaporwareMichael S2021/03/23 01:58 PM
          The Mill = vaporwareCarson2021/03/23 06:17 PM
          The Mill = doomed but interestingAndrew Clough2021/03/24 08:06 AM
            Solution in search of a problemwumpus2021/03/24 08:52 AM
              Solution in search of a problemdmcq2021/03/24 10:22 AM
          never-ware != vaporware (at least in connotation)Paul A. Clayton2021/03/24 10:37 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anonini2021/03/22 08:28 AM
    microcode that can combine instructionMoritz2021/03/22 12:26 PM
  What are your ideas for a radically different CPU ISA + physical Arch?anony2021/03/22 10:16 AM
    Totally clueless.Heikki Kultala2021/03/22 05:53 PM
  Hierarchical instruction setHeikki Kultala2021/03/22 06:52 PM
    Hierarchical instruction setVeedrac2021/03/23 03:49 AM
      Hierarchical instruction setHeikki Kultala2021/03/23 06:46 AM
        Hierarchical instruction setEtienne Lorrain2021/03/23 07:16 AM
          microthreads on OS call/exceptionHeikki Kultala2021/03/23 07:34 AM
        Hierarchical instruction setVeedrac2021/03/23 09:31 AM
          Hierarchical instruction setEtienne Lorrain2021/03/24 01:13 AM
            Hierarchical instruction setVeedrac2021/03/24 07:11 AM
    Hierarchical instruction setAnon2021/03/23 08:39 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Paul A. Clayton2021/03/26 08:21 AM
    What are your ideas for a radically different CPU ISA + physical Arch?wumpus2021/03/26 09:45 AM
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