rwessel (rwessel.delete@this.yahoo.com) on March 21, 2021 10:47 pm wrote:
> anon2 (anon.delete@this.anon.com) on March 21, 2021 7:08 pm wrote:
> > rwessel (rwessel.delete@this.yahoo.com) on March 21, 2021 5:05 am wrote:
> > > anon2 (anon.delete@this.anon.com) on March 21, 2021 4:52 am wrote:
> > > > anon (anon.delete@this.anon.com) on March 21, 2021 3:22 am wrote:
> > > > > Hugo Décharnes (hdecharn.delete@this.outlook.fr) on March 20, 2021 7:34 am wrote:
> > > > > > Having programs delivered in annotated, intermediate representation (IR) would be great. When compiled
> > > > > > to a specific ISA, removing instructions is impossible, while adding new ones does not benefit the already
> > > > > > compiled programs.
> > > > >
> > > > > I think you are a bit late to the party. Software has been distributed using IR and then
> > > > > compiled/JITed on the target machine for over two decades now... just look at Java and
> > > > > .NET applications. And even if you counter that it's something different as these target
> > > > > a virtual machine rather than the "real" hardware, here are some other examples:
> > > > >
> > > > > - Compiled GPU shaders on virtually every platform
> > > > > - Apple has been distributing iOS software as LLVM bytecode since 2015
> > > > > - WASM
> > > >
> > > > Over 3 decades with OS/400.
> > >
> > >
> > > S/38 shipped in 1978.
> >
> > Ah true, so 4 decades now. As far as I know, they switched to a quite radically different
> > architecture (PowerPC) albeit with some added hardware features to improve performance
> > of the result (although these may have been less about the shipped intermediate code in
> > general, and more about the specific single address space nature of the system.
>
>
> S/38-AS/400-IBM i changed the native ISA several times in the S/38 and early
> AS/400 eras, until they settled on PPC with the model 400s, IIRC.
>
> The MI code continued to run through all that.
>
> The extensions to PPC were fairly modest. Basically a tag bit got added to each word (4/8/16 bytes, depending
> on model), and stored in the ECC bits. Normal stores would clear the tag bits. But in "Tags Active" mode,
> STQ would copy the tag bit from a bit in XER. That could then be checked at load time (LQ would load the
> tag bit into the bit in XER in TA mode, and you could test that), and thus prevent pointers or capabilities
> from being used if they were modified. A few other instructions and small operational changes were added,
> as well as a funky system call instruction, if you enabled "TA" mode in an MSR.

I saw another project which was considering storing a tag bit in the ECC as an alternative to having it separate, I just thought WTF about it but didn't enquire further but obviously they must have a way of making it work. I just don't see how it can be done without compromising the whole ECC system - have you a link to something about it thanks?