Deliver programs in IR

By: rwessel (rwessel.delete@this.yahoo.com), March 22, 2021 5:27 am
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on March 22, 2021 4:33 am wrote:
> rwessel (rwessel.delete@this.yahoo.com) on March 21, 2021 10:47 pm wrote:
> > anon2 (anon.delete@this.anon.com) on March 21, 2021 7:08 pm wrote:
> > > rwessel (rwessel.delete@this.yahoo.com) on March 21, 2021 5:05 am wrote:
> > > > anon2 (anon.delete@this.anon.com) on March 21, 2021 4:52 am wrote:
> > > > > anon (anon.delete@this.anon.com) on March 21, 2021 3:22 am wrote:
> > > > > > Hugo Décharnes (hdecharn.delete@this.outlook.fr) on March 20, 2021 7:34 am wrote:
> > > > > > > Having programs delivered in annotated, intermediate representation (IR) would be great. When compiled
> > > > > > > to a specific ISA, removing instructions is impossible, while adding new ones does not benefit the already
> > > > > > > compiled programs.
> > > > > >
> > > > > > I think you are a bit late to the party. Software has been distributed using IR and then
> > > > > > compiled/JITed on the target machine for over two decades now... just look at Java and
> > > > > > .NET applications. And even if you counter that it's something different as these target
> > > > > > a virtual machine rather than the "real" hardware, here are some other examples:
> > > > > >
> > > > > > - Compiled GPU shaders on virtually every platform
> > > > > > - Apple has been distributing iOS software as LLVM bytecode since 2015
> > > > > > - WASM
> > > > >
> > > > > Over 3 decades with OS/400.
> > > >
> > > >
> > > > S/38 shipped in 1978.
> > >
> > > Ah true, so 4 decades now. As far as I know, they switched to a quite radically different
> > > architecture (PowerPC) albeit with some added hardware features to improve performance
> > > of the result (although these may have been less about the shipped intermediate code in
> > > general, and more about the specific single address space nature of the system.
> >
> >
> > S/38-AS/400-IBM i changed the native ISA several times in the S/38 and early
> > AS/400 eras, until they settled on PPC with the model 400s, IIRC.
> >
> > The MI code continued to run through all that.
> >
> > The extensions to PPC were fairly modest. Basically a tag
> > bit got added to each word (4/8/16 bytes, depending
> > on model), and stored in the ECC bits. Normal stores would clear the tag bits. But in "Tags Active" mode,
> > STQ would copy the tag bit from a bit in XER. That could then be checked at load time (LQ would load the
> > tag bit into the bit in XER in TA mode, and you could test that), and thus prevent pointers or capabilities
> > from being used if they were modified. A few other instructions and small operational changes were added,
> > as well as a funky system call instruction, if you enabled "TA" mode in an MSR.
>
> I saw another project which was considering storing a tag bit in the ECC as an alternative
> to having it separate, I just thought WTF about it but didn't enquire further but obviously
> they must have a way of making it work. I just don't see how it can be done without compromising
> the whole ECC system - have you a link to something about it thanks?


Most ECC schemes have some extra space. For example, tradition SECDED on 64 bit words has about .83 bits "extra" space relative to what's required for single bit correction and double bit detection. If you applied traditional SECDED to 128 bit memory words, you'd have a full seven bits unused (plus a partial bit in the 9 bit ECC).

Of course in the SECDED/128-bit case you could do better than SECDEC by actually using those extra bits - single error correction and 8 bit detection would be possible. Obviously you could instead use one of those bits for the tag, and still get 7 bit detection.

Many of the more sophisticated schemes (chip-kill and the like) have even greater overhead.

But stuffing some sort of tag into the ECC inherently involves weakening the (potential) level of protection. Exactly how much weaker is acceptable is going to depend on the application. You could, for example, spread your tags over two 64/72 memory words (with normal-ish SECDED), where you have about 1.6 bits to play with without weakening SECDED, or decide that single error correction, (most) double error detection is good enough.

Really efficiently using those fractional bits can be quite a bit of work, though, so it's often easier just to have enough "free" bits that you can uses in a straight-forward way. For example, an implementation could just make the physical word a bit wider - a 73 bit physical memory word would allow you to implement either SECTED, or SECDED with a tag bit. Weird memory widths were more common in the older days, though, now almost everything is built out of standard DIMMs (I believe the pre-PPC S/38 and AS/400s took that route).

While not directly applicable to general memory tagging (where you need to be able to tag any memory word, containing any value), the presence of "code violations" is also potentially useful. For example, with 64/72 memory and SECDED, you could store 2**64 "normal" values, or 2**63.83 "special" (tagged) values. CVs are common in communications, where they're used for in-band signaling, frame delimiters and such.

I don't know exactly what IBM did with PPC AS, but the architecture requires one tag bit on each 128 bit memory word, but doesn't define how that's physically stored.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
What are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 04:21 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Stanislav Shwartsman2021/03/20 05:22 AM
    I like the analysis of current arch presentedMoritz2021/03/20 09:13 AM
    Did you read this old article?Michael S2021/03/21 01:12 AM
  Deliver programs in IRHugo Décharnes2021/03/20 06:34 AM
    Java bytecode and Wasm exist, why invent something else? (NT)Foo_2021/03/20 07:01 AM
      Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 07:55 AM
        Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 09:50 AM
          Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 11:40 AM
            Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 03:54 PM
              It's called source code, no?anonymou52021/03/20 11:43 PM
                It's called source code, no?Foo_2021/03/21 04:07 AM
                Thoughts on software distribution formatsPaul A. Clayton2021/03/22 12:45 PM
    Deliver programs in IRJames2021/03/20 10:24 AM
      Deliver programs in IRHugo Décharnes2021/03/20 11:28 AM
        Deliver programs in IRHugo Décharnes2021/03/20 11:36 AM
    Deliver programs in IRLinus Torvalds2021/03/20 12:20 PM
      Deliver programs in IRHugo Décharnes2021/03/20 12:51 PM
      I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/20 04:49 PM
        I'd like to be able to NOT specify order for some things ...Jukka Larja2021/03/20 11:26 PM
          NOT (unintentionally) specify orderMoritz2021/03/21 05:00 AM
            NOT (unintentionally) specify orderJukka Larja2021/03/22 06:11 AM
              NOT (unintentionally) specify orderMoritz2021/03/22 11:40 AM
                NOT (unintentionally) specify orderJukka Larja2021/03/23 05:26 AM
          I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/21 08:47 AM
            I'd like to be able to NOT specify order for some things ...Victor Alander2021/03/21 04:14 PM
      Next architecture will start with MLwumpus2021/03/21 11:24 AM
        Next architecture will start with MLLinus Torvalds2021/03/21 01:38 PM
          Maybe SQL was the better example for general purpose machineswumpus2021/03/22 07:33 AM
            Maybe SQL was the better example for general purpose machinesanon2021/03/22 08:10 AM
        Next architecture will start with MLML will move to PIM2021/03/22 02:51 AM
    Deliver programs in IRanon2021/03/21 02:22 AM
      Deliver programs in IRanon22021/03/21 03:52 AM
        Deliver programs in IRrwessel2021/03/21 04:05 AM
          Deliver programs in IRanon22021/03/21 06:08 PM
            Deliver programs in IRrwessel2021/03/21 09:47 PM
              Deliver programs in IRdmcq2021/03/22 03:33 AM
                Deliver programs in IRrwessel2021/03/22 05:27 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Veedrac2021/03/20 10:27 AM
    Cray MTAanon2021/03/20 05:04 PM
      Cray MTAChester2021/03/20 06:54 PM
        Cray MTAVeedrac2021/03/21 12:33 AM
          Cray MTAnoone2021/03/21 08:15 AM
            Cray MTAVeedrac2021/03/21 09:54 AM
    monolithic 3Dwumpus2021/03/21 11:50 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Anon2021/03/20 11:06 PM
  What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 04:02 AM
  What are your ideas for a radically different CPU ISA + physical Arch?juanrga2021/03/21 04:46 AM
  Summery so farMoritz2021/03/21 08:45 AM
    Summery so farrwessel2021/03/21 10:23 AM
      not staticMoritz2021/03/26 09:12 AM
        Dynamic meta instruction encoding for instruction window compressionMoritz2021/03/28 02:28 AM
          redistributing the work between static compiler, dynamic compiler, CPUMoritz2021/04/05 02:21 AM
            redistributing the work between static compiler, dynamic compiler, CPUdmcq2021/04/05 08:27 AM
    Summery so farAnon2021/03/21 07:53 PM
  What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 09:10 AM
    What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 10:26 AM
      What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 10:34 AM
        What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 11:55 AM
          What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 12:31 PM
      What are your ideas for a radically different CPU ISA + physical Arch?gallier22021/03/21 11:49 PM
  What are your ideas for a radically different CPU ISA + physical Arch?dmcq2021/03/21 02:50 PM
  Microthread/low IPCEtienne Lorrain2021/03/22 02:22 AM
    Microthread/low IPCdmcq2021/03/22 03:24 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 05:10 AM
        Microthread/low IPCdmcq2021/03/22 07:24 AM
    Microthread/low IPCdmcq2021/03/22 03:53 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 04:46 AM
      Microthread/low IPCAnon2021/03/22 04:47 AM
    Microthread/low IPCHeikki Kultala2021/03/22 04:47 PM
      Microthread/low IPCEtienne Lorrain2021/03/23 02:36 AM
        Microthread/low IPCNyan2021/03/24 02:00 AM
          Microthread/low IPCEtienne Lorrain2021/03/24 03:23 AM
      Microthread/low IPCAnon2021/03/23 07:16 AM
        Microthread/low IPCgai2021/03/23 08:37 AM
          Microthread/low IPCAnon2021/03/23 09:17 AM
            Microthread/low IPCdmcq2021/03/23 11:42 AM
  Have you looked at "The Mill CPU" project? (nt)Anon C2021/03/22 05:21 AM
    Have you looked at "The Mill CPU" project? (nt)Moritz2021/03/22 11:13 AM
      Have you looked at "The Mill CPU" project? (nt)Andrew Clough2021/03/22 03:27 PM
        The Mill = vaporwareRichardC2021/03/23 11:47 AM
          The Mill = vaporwareMichael S2021/03/23 12:58 PM
          The Mill = vaporwareCarson2021/03/23 05:17 PM
          The Mill = doomed but interestingAndrew Clough2021/03/24 07:06 AM
            Solution in search of a problemwumpus2021/03/24 07:52 AM
              Solution in search of a problemdmcq2021/03/24 09:22 AM
          never-ware != vaporware (at least in connotation)Paul A. Clayton2021/03/24 09:37 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anonini2021/03/22 07:28 AM
    microcode that can combine instructionMoritz2021/03/22 11:26 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anony2021/03/22 09:16 AM
    Totally clueless.Heikki Kultala2021/03/22 04:53 PM
  Hierarchical instruction setHeikki Kultala2021/03/22 05:52 PM
    Hierarchical instruction setVeedrac2021/03/23 02:49 AM
      Hierarchical instruction setHeikki Kultala2021/03/23 05:46 AM
        Hierarchical instruction setEtienne Lorrain2021/03/23 06:16 AM
          microthreads on OS call/exceptionHeikki Kultala2021/03/23 06:34 AM
        Hierarchical instruction setVeedrac2021/03/23 08:31 AM
          Hierarchical instruction setEtienne Lorrain2021/03/24 12:13 AM
            Hierarchical instruction setVeedrac2021/03/24 06:11 AM
    Hierarchical instruction setAnon2021/03/23 07:39 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Paul A. Clayton2021/03/26 07:21 AM
    What are your ideas for a radically different CPU ISA + physical Arch?wumpus2021/03/26 08:45 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell avocado?