Microthread/low IPC

By: dmcq (dmcq.delete@this.fano.co.uk), March 22, 2021 7:24 am
Room: Moderated Discussions
Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on March 22, 2021 6:10 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on March 22, 2021 4:24 am wrote:
> > Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on March 22, 2021 3:22 am wrote:
> > > ...
> > > On a more complete redesign of a processor, I would easily "type" the registers of the processor (as I have
> > > said in old threads), i.e. have assembly instructions to change the type of each registers at run time.
> > > I imagine processor registers could have types like:
> > > - simple byte/word/long or any fixed number of bits like all processors
> > > - pointer to memory (probably 64 bits), maybe with read-only/write-only/read-write
> > > distinction (would help cache prefetch for read or write at value initialisation)
> > > - Integer/unsigned which would saturate on overflows, or bitmasks types
> > > - floating point of fixed number of bits
> > > - vector of byte/word/long/floats...
> > > At least it would reduce the number of instructions (addb, addw, addl, ...), clearly define when a register
> > > is live or dead, and give more context to the core executor. At first one could fix all registers being
> > > 64 bits to use standard current compilers, and implement other types slowly, one at a time.
> >
> > Well I know of one ISA that did a simple form of that - the length of the operation was set by the
> > load and then operations like add worked at that length. The operations were mostly register-memory
> > so savig a bit mattered but you wouldn't save much with risc except for a compressed version.
> >
>
> Adding 1 to a byte involves a mask with 0xFF on RISC (most of the time).
> Adding 1 to a vector of 4 bytes inside a register is not the same a adding 0x01010101 to a 32 bits register.
> I see quite a few possible improvements by giving more to do to the "core executor"
> (i.e. mostly ALU) in each cycles, even if that slows down slightly the cycle time.
> And having a more orthogonal instructions set is not a bad thing.
> The advantage of this very big change (typing registers) would be that one can
> fix their type at boot for first introduction/tests, and proceed one per one
> each type (getting prefetch right when an address register is initialised)

The only real problem I can see with the idea is saving and restoring registers in a procedure entry and exit. The one I was talking about was basically stack based and didn't do that and the length was stored in the program status word. In a straightforward implementation one would have to allocate the largest size and more nd have a special load and store instructions for them. Or somthing like SPARC's register banks.

The amount that may need to be saved switching from one process to another is growing and calling procedure is a smaller but more frequent version of that. And it would be nice if the values are never even stored away if the original environment is restored quickly. If this problem could be solved in a really nice way then the problem of the extra space for tagged registers might to a large extent disappear.
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What are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 04:21 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Stanislav Shwartsman2021/03/20 05:22 AM
    I like the analysis of current arch presentedMoritz2021/03/20 09:13 AM
    Did you read this old article?Michael S2021/03/21 01:12 AM
  Deliver programs in IRHugo Décharnes2021/03/20 06:34 AM
    Java bytecode and Wasm exist, why invent something else? (NT)Foo_2021/03/20 07:01 AM
      Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 07:55 AM
        Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 09:50 AM
          Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 11:40 AM
            Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 03:54 PM
              It's called source code, no?anonymou52021/03/20 11:43 PM
                It's called source code, no?Foo_2021/03/21 04:07 AM
                Thoughts on software distribution formatsPaul A. Clayton2021/03/22 12:45 PM
    Deliver programs in IRJames2021/03/20 10:24 AM
      Deliver programs in IRHugo Décharnes2021/03/20 11:28 AM
        Deliver programs in IRHugo Décharnes2021/03/20 11:36 AM
    Deliver programs in IRLinus Torvalds2021/03/20 12:20 PM
      Deliver programs in IRHugo Décharnes2021/03/20 12:51 PM
      I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/20 04:49 PM
        I'd like to be able to NOT specify order for some things ...Jukka Larja2021/03/20 11:26 PM
          NOT (unintentionally) specify orderMoritz2021/03/21 05:00 AM
            NOT (unintentionally) specify orderJukka Larja2021/03/22 06:11 AM
              NOT (unintentionally) specify orderMoritz2021/03/22 11:40 AM
                NOT (unintentionally) specify orderJukka Larja2021/03/23 05:26 AM
          I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/21 08:47 AM
            I'd like to be able to NOT specify order for some things ...Victor Alander2021/03/21 04:14 PM
      Next architecture will start with MLwumpus2021/03/21 11:24 AM
        Next architecture will start with MLLinus Torvalds2021/03/21 01:38 PM
          Maybe SQL was the better example for general purpose machineswumpus2021/03/22 07:33 AM
            Maybe SQL was the better example for general purpose machinesanon2021/03/22 08:10 AM
        Next architecture will start with MLML will move to PIM2021/03/22 02:51 AM
    Deliver programs in IRanon2021/03/21 02:22 AM
      Deliver programs in IRanon22021/03/21 03:52 AM
        Deliver programs in IRrwessel2021/03/21 04:05 AM
          Deliver programs in IRanon22021/03/21 06:08 PM
            Deliver programs in IRrwessel2021/03/21 09:47 PM
              Deliver programs in IRdmcq2021/03/22 03:33 AM
                Deliver programs in IRrwessel2021/03/22 05:27 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Veedrac2021/03/20 10:27 AM
    Cray MTAanon2021/03/20 05:04 PM
      Cray MTAChester2021/03/20 06:54 PM
        Cray MTAVeedrac2021/03/21 12:33 AM
          Cray MTAnoone2021/03/21 08:15 AM
            Cray MTAVeedrac2021/03/21 09:54 AM
    monolithic 3Dwumpus2021/03/21 11:50 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Anon2021/03/20 11:06 PM
  What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 04:02 AM
  What are your ideas for a radically different CPU ISA + physical Arch?juanrga2021/03/21 04:46 AM
  Summery so farMoritz2021/03/21 08:45 AM
    Summery so farrwessel2021/03/21 10:23 AM
      not staticMoritz2021/03/26 09:12 AM
        Dynamic meta instruction encoding for instruction window compressionMoritz2021/03/28 02:28 AM
          redistributing the work between static compiler, dynamic compiler, CPUMoritz2021/04/05 02:21 AM
            redistributing the work between static compiler, dynamic compiler, CPUdmcq2021/04/05 08:27 AM
    Summery so farAnon2021/03/21 07:53 PM
  What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 09:10 AM
    What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 10:26 AM
      What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 10:34 AM
        What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 11:55 AM
          What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 12:31 PM
      What are your ideas for a radically different CPU ISA + physical Arch?gallier22021/03/21 11:49 PM
  What are your ideas for a radically different CPU ISA + physical Arch?dmcq2021/03/21 02:50 PM
  Microthread/low IPCEtienne Lorrain2021/03/22 02:22 AM
    Microthread/low IPCdmcq2021/03/22 03:24 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 05:10 AM
        Microthread/low IPCdmcq2021/03/22 07:24 AM
    Microthread/low IPCdmcq2021/03/22 03:53 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 04:46 AM
      Microthread/low IPCAnon2021/03/22 04:47 AM
    Microthread/low IPCHeikki Kultala2021/03/22 04:47 PM
      Microthread/low IPCEtienne Lorrain2021/03/23 02:36 AM
        Microthread/low IPCNyan2021/03/24 02:00 AM
          Microthread/low IPCEtienne Lorrain2021/03/24 03:23 AM
      Microthread/low IPCAnon2021/03/23 07:16 AM
        Microthread/low IPCgai2021/03/23 08:37 AM
          Microthread/low IPCAnon2021/03/23 09:17 AM
            Microthread/low IPCdmcq2021/03/23 11:42 AM
  Have you looked at "The Mill CPU" project? (nt)Anon C2021/03/22 05:21 AM
    Have you looked at "The Mill CPU" project? (nt)Moritz2021/03/22 11:13 AM
      Have you looked at "The Mill CPU" project? (nt)Andrew Clough2021/03/22 03:27 PM
        The Mill = vaporwareRichardC2021/03/23 11:47 AM
          The Mill = vaporwareMichael S2021/03/23 12:58 PM
          The Mill = vaporwareCarson2021/03/23 05:17 PM
          The Mill = doomed but interestingAndrew Clough2021/03/24 07:06 AM
            Solution in search of a problemwumpus2021/03/24 07:52 AM
              Solution in search of a problemdmcq2021/03/24 09:22 AM
          never-ware != vaporware (at least in connotation)Paul A. Clayton2021/03/24 09:37 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anonini2021/03/22 07:28 AM
    microcode that can combine instructionMoritz2021/03/22 11:26 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anony2021/03/22 09:16 AM
    Totally clueless.Heikki Kultala2021/03/22 04:53 PM
  Hierarchical instruction setHeikki Kultala2021/03/22 05:52 PM
    Hierarchical instruction setVeedrac2021/03/23 02:49 AM
      Hierarchical instruction setHeikki Kultala2021/03/23 05:46 AM
        Hierarchical instruction setEtienne Lorrain2021/03/23 06:16 AM
          microthreads on OS call/exceptionHeikki Kultala2021/03/23 06:34 AM
        Hierarchical instruction setVeedrac2021/03/23 08:31 AM
          Hierarchical instruction setEtienne Lorrain2021/03/24 12:13 AM
            Hierarchical instruction setVeedrac2021/03/24 06:11 AM
    Hierarchical instruction setAnon2021/03/23 07:39 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Paul A. Clayton2021/03/26 07:21 AM
    What are your ideas for a radically different CPU ISA + physical Arch?wumpus2021/03/26 08:45 AM
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