I always liked the idea of a JITed architecture. That is the system actually profiles what is happening and can tailor the ISA to the currently running workload. For example by fusing common patterns and reconfigure the hardware to add macro instructions that implement that particular pattern. Or it could reconfigure the port configuration to be more tailored for the specific workloads. Or redistribute internal buffer and queues over different arrays depending on which buffes are used most.

There are some "ahead of the time" compilers to do custom ISAs for specific workloads, but nothing done truly at run time as far as I know. This could be combined with software level optimizations at run time of course.

This would require somewhat reconfigurable hardware. This doesn't necessarily mean a full FPGA, but at least a flexible way to reconfigure instruction units, e.g. using a graph execution model, or perhaps some variant of fast microcode that can combine instruction units.