I see it as moving the dispatcher as far out as possible and taking advantage of various accelerators to get it done as best as possible at the lowest power. Poll your devices for power/heat/load capability and instruction set. FPGA to handle the juggling, and tweak from there. You do want a small "general purpose" RISC to handle all your small low power tasks, but that's it, integer heavy to external unit. Memory at every device, managed by the FPGA. Speculation needs the axe, provide hints to appropriate acceleration device instead (para/serial/and maybe memory type fast/wide).

Ironically, everyone else is waiting for Intel to roll over and die, but between their acquisitions over the years and their upcoming designs. I see it.