By: Moritz (better.delete@this.not.tell), March 22, 2021 12:26 pm
Room: Moderated Discussions
anonini (anon.delete@this.anon.com) on March 22, 2021 8:28 am wrote:
> I always liked the idea of a JITed architecture. That is the system actually profiles what is happening
> and can tailor the ISA to the currently running workload. For example by fusing common patterns and
> reconfigure the hardware to add macro instructions that implement that particular pattern. Or it could
> reconfigure the port configuration to be more tailored for the specific workloads. Or redistribute
> internal buffer and queues over different arrays depending on which buffers are used most.
> There are some "ahead of the time" compilers to do custom ISAs for specific
> workloads, but nothing done truly at run time as far as I know. This could
> be combined with software level optimizations at run time of course.
> This would require somewhat reconfigurable hardware. This doesn't necessarily mean a full FPGA,
> but at least a flexible way to reconfigure instruction units, e.g. using a graph execution
> model, or perhaps some variant of fast microcode that can combine instruction units.
That is the direction I am thinking in as well. I do not think it takes anything like an FPGA, a general purpose processor is configurable. If it were fed calls to independent code blocks (micro-threads) with the data to use, that would free the execution window of entries.
Instead of a bigger instruction window the instructions inside the window could encode more work.
> I always liked the idea of a JITed architecture. That is the system actually profiles what is happening
> and can tailor the ISA to the currently running workload. For example by fusing common patterns and
> reconfigure the hardware to add macro instructions that implement that particular pattern. Or it could
> reconfigure the port configuration to be more tailored for the specific workloads. Or redistribute
> internal buffer and queues over different arrays depending on which buffers are used most.
> There are some "ahead of the time" compilers to do custom ISAs for specific
> workloads, but nothing done truly at run time as far as I know. This could
> be combined with software level optimizations at run time of course.
> This would require somewhat reconfigurable hardware. This doesn't necessarily mean a full FPGA,
> but at least a flexible way to reconfigure instruction units, e.g. using a graph execution
> model, or perhaps some variant of fast microcode that can combine instruction units.
That is the direction I am thinking in as well. I do not think it takes anything like an FPGA, a general purpose processor is configurable. If it were fed calls to independent code blocks (micro-threads) with the data to use, that would free the execution window of entries.
Instead of a bigger instruction window the instructions inside the window could encode more work.
