Hierarchical instruction set

By: Heikki Kultala (heikk.i.kultal.a.delete@this.gmail.com), March 23, 2021 6:46 am
Room: Moderated Discussions
Veedrac (ignore.delete@this.this.com) on March 23, 2021 3:49 am wrote:
> Heikki Kultala (heikki.kultal.a.delete@this.gmail.com) on March 22, 2021 6:52 pm wrote:
> >
> > The implementation is always free to execute the microthreads sequentially (common case if all our
> > hardware microthreads are already in use, for example started by outer level function); programmer
> > can write his code/compiler can compile the code like he/it has infinite amount of microthreads
> > available. As the bundles execute atomically, different microthreads can still do things like incrementing
> > the same counter in memory, but as they are allowed to execute sequentially, they are not allowed
> > to wait data from one another microthread because that might cause a deadlock.
>
> Personally I expect this to be very limiting because it means you must spawn microthreads at the
> top level in an order that completely the respects dependencies of all the sub-threads.

These are not meant to be spawned at the top level at all. At top level, you spawn normal threads and execute those on totally different cores.

These are meant for a limited thing. They are only meant to be a slight bonus on top of a core that has excellent per-thread-performance by other means.

These microthreads are for only fully parallel very small things, meant to be used in very small granularity. These are not meant to be replacing normal threads on existing code but to be used for things where threads currently cannot be used because of the overheads. And typically inserted automatically by the compiler.

For example, if you have a (small) fully data parallel for loop, In addition to vectorizing it, you may also split it into 2-4 parts and launch a microthread for each part. Compared to normal threads, the benefit of these microthreads is much smaller overhead so that there is no need to analyze if the loop has big enough iteration cont for the threading to be beneficial, accelerate those cases when the iteration count is quite small.

Or you call some same pure function (which takes like 50 clock cycles) couple of times with different parameters, you can spawn a separate microthread for each function call.


But maybe some kind of unidirectional data flow could be allowed. Have to think how this would work when there are more than N+1 microthreads (where N is the limit of executing at the the same time)


> This is
> a lot to pay when ROBs already show us that hardware is amazing at handling register wakeups.

What is lot to pay?

> You can avoid deadlocks by requiring inter-thread dependencies to be a DAG.

Yes, a good idea, maybe it can be decided that data can flow to exactly one direction between the thread pair. However, I'm afraid that this would get more complicated with more than 2 threads.

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TopicPosted ByDate
What are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 05:21 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Stanislav Shwartsman2021/03/20 06:22 AM
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    Did you read this old article?Michael S2021/03/21 02:12 AM
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      Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 08:55 AM
        Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 10:50 AM
          Java bytecode and Wasm exist, why invent something else?Hugo Décharnes2021/03/20 12:40 PM
            Java bytecode and Wasm exist, why invent something else?Foo_2021/03/20 04:54 PM
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                It's called source code, no?Foo_2021/03/21 05:07 AM
                Thoughts on software distribution formatsPaul A. Clayton2021/03/22 01:45 PM
    Deliver programs in IRJames2021/03/20 11:24 AM
      Deliver programs in IRHugo Décharnes2021/03/20 12:28 PM
        Deliver programs in IRHugo Décharnes2021/03/20 12:36 PM
    Deliver programs in IRLinus Torvalds2021/03/20 01:20 PM
      Deliver programs in IRHugo Décharnes2021/03/20 01:51 PM
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        I'd like to be able to NOT specify order for some things ...Jukka Larja2021/03/21 12:26 AM
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            NOT (unintentionally) specify orderJukka Larja2021/03/22 07:11 AM
              NOT (unintentionally) specify orderMoritz2021/03/22 12:40 PM
                NOT (unintentionally) specify orderJukka Larja2021/03/23 06:26 AM
          I'd like to be able to NOT specify order for some things ...Mark Roulo2021/03/21 09:47 AM
            I'd like to be able to NOT specify order for some things ...Victor Alander2021/03/21 05:14 PM
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            Maybe SQL was the better example for general purpose machinesanon2021/03/22 09:10 AM
        Next architecture will start with MLML will move to PIM2021/03/22 03:51 AM
    Deliver programs in IRanon2021/03/21 03:22 AM
      Deliver programs in IRanon22021/03/21 04:52 AM
        Deliver programs in IRrwessel2021/03/21 05:05 AM
          Deliver programs in IRanon22021/03/21 07:08 PM
            Deliver programs in IRrwessel2021/03/21 10:47 PM
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                Deliver programs in IRrwessel2021/03/22 06:27 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Veedrac2021/03/20 11:27 AM
    Cray MTAanon2021/03/20 06:04 PM
      Cray MTAChester2021/03/20 07:54 PM
        Cray MTAVeedrac2021/03/21 01:33 AM
          Cray MTAnoone2021/03/21 09:15 AM
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    Summery so farrwessel2021/03/21 11:23 AM
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          redistributing the work between static compiler, dynamic compiler, CPUMoritz2021/04/05 03:21 AM
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    Summery so farAnon2021/03/21 08:53 PM
  What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 10:10 AM
    What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 11:26 AM
      What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 11:34 AM
        What are your ideas for a radically different CPU ISA + physical Arch?blaine2021/03/21 12:55 PM
          What are your ideas for a radically different CPU ISA + physical Arch?rwessel2021/03/21 01:31 PM
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  What are your ideas for a radically different CPU ISA + physical Arch?dmcq2021/03/21 03:50 PM
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    Microthread/low IPCdmcq2021/03/22 04:24 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 06:10 AM
        Microthread/low IPCdmcq2021/03/22 08:24 AM
    Microthread/low IPCdmcq2021/03/22 04:53 AM
      Microthread/low IPCEtienne Lorrain2021/03/22 05:46 AM
      Microthread/low IPCAnon2021/03/22 05:47 AM
    Microthread/low IPCHeikki Kultala2021/03/22 05:47 PM
      Microthread/low IPCEtienne Lorrain2021/03/23 03:36 AM
        Microthread/low IPCNyan2021/03/24 03:00 AM
          Microthread/low IPCEtienne Lorrain2021/03/24 04:23 AM
      Microthread/low IPCAnon2021/03/23 08:16 AM
        Microthread/low IPCgai2021/03/23 09:37 AM
          Microthread/low IPCAnon2021/03/23 10:17 AM
            Microthread/low IPCdmcq2021/03/23 12:42 PM
  Have you looked at "The Mill CPU" project? (nt)Anon C2021/03/22 06:21 AM
    Have you looked at "The Mill CPU" project? (nt)Moritz2021/03/22 12:13 PM
      Have you looked at "The Mill CPU" project? (nt)Andrew Clough2021/03/22 04:27 PM
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          never-ware != vaporware (at least in connotation)Paul A. Clayton2021/03/24 10:37 AM
  What are your ideas for a radically different CPU ISA + physical Arch?anonini2021/03/22 08:28 AM
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  What are your ideas for a radically different CPU ISA + physical Arch?anony2021/03/22 10:16 AM
    Totally clueless.Heikki Kultala2021/03/22 05:53 PM
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    Hierarchical instruction setVeedrac2021/03/23 03:49 AM
      Hierarchical instruction setHeikki Kultala2021/03/23 06:46 AM
        Hierarchical instruction setEtienne Lorrain2021/03/23 07:16 AM
          microthreads on OS call/exceptionHeikki Kultala2021/03/23 07:34 AM
        Hierarchical instruction setVeedrac2021/03/23 09:31 AM
          Hierarchical instruction setEtienne Lorrain2021/03/24 01:13 AM
            Hierarchical instruction setVeedrac2021/03/24 07:11 AM
    Hierarchical instruction setAnon2021/03/23 08:39 AM
  What are your ideas for a radically different CPU ISA + physical Arch?Paul A. Clayton2021/03/26 08:21 AM
    What are your ideas for a radically different CPU ISA + physical Arch?wumpus2021/03/26 09:45 AM
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