By: Anon (no.delete@this.spam.com), March 23, 2021 10:17 am
Room: Moderated Discussions
gai (gai.delete@this.n.o) on March 23, 2021 9:37 am wrote:
> In the worst cases, an instruction's operand size might change major properties like
> latency or uop sequencing. These are things that should be known earlier than execution.
> Many of the cases may involve FP or SIMD registers, but complex scalar integer instructions,
> such as multiplication and division, may also use size-dependent latency or microcoding.
This is true for multiply, but for the others:
- SIMD use another unit any way, and another register set;
- Division is variable latency anyway.
Dealing with MUL is no big deal after you already solved all other issues.
> In the worst cases, an instruction's operand size might change major properties like
> latency or uop sequencing. These are things that should be known earlier than execution.
> Many of the cases may involve FP or SIMD registers, but complex scalar integer instructions,
> such as multiplication and division, may also use size-dependent latency or microcoding.
This is true for multiply, but for the others:
- SIMD use another unit any way, and another register set;
- Division is variable latency anyway.
Dealing with MUL is no big deal after you already solved all other issues.