Anon (no.delete@this.spam.com) on March 23, 2021 10:17 am wrote:
> gai (gai.delete@this.n.o) on March 23, 2021 9:37 am wrote:
> > In the worst cases, an instruction's operand size might change major properties like
> > latency or uop sequencing. These are things that should be known earlier than execution.
> > Many of the cases may involve FP or SIMD registers, but complex scalar integer instructions,
> > such as multiplication and division, may also use size-dependent latency or microcoding.
>
> This is true for multiply, but for the others:
> - SIMD use another unit any way, and another register set;
> - Division is variable latency anyway.
>
> Dealing with MUL is no big deal after you already solved all other issues.

There's no reason the types and lengths can't be dealt with quickly at instruction decode time. The only problem I see is that if decoding a number of instructions at a time there would need to be a bypass so if an instruction sets a register type it is taken account of quickly by later instructions in the same block rather than just being read from a table. Basically an extension of the register dependency problem.