By: David Hess (davidwhess.delete@this.gmail.com), April 5, 2021 8:26 pm
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on April 5, 2021 11:31 am wrote:
> Doug S (foo.delete@this.bar.bar) on April 5, 2021 6:57 am wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on April 4, 2021 8:45 pm wrote:
> > > This also means that the external overhead of ECC is greater going from 64/72 to 32/40,
> > > but maybe the internal organization is different for the mandatory internal ECC.
> >
> >
> > Given that full ECC for DDR5 will (at least) double the ECC DIMM price penalty I wouldn't be
> > surprised to see some using DDR5's internal ECC as an excuse to drop board support for it. Fewer
> > customers will demand it due to the higher cost, and marketing will be telling those customers
> > "its built into the DIMMs now, you don't need ECC except at the extreme high end".
> >
> > Less demand for it will mean those ECC DIMMs have an even greater price penalty above the 25%
> > raw cost than DDR4 ECC is above the 12.5% raw cost, which is why I should "at least" above.
> >
> > DDR5's internal ECC is 128 bits wide, so the bit penalty is kept pretty low.
>
> There is no cost difference.
>
> Anyway, everybody today read the entire cacheline, that is 512 bits
> with the extra 64 bits for ECC, that doesn't change with DDR5.
Transfers are done in 64 byte or 512 bit cache line sized chunks, but ECC is implemented on 128/144 or 256/288 words. 512/576 could be done but I have never seen it. The larger words have the advantage of supporting x4 chipkill and such improvements.
For DDR5 the internal ECC is 128/136 which can only correct single bit errors, and it is *not* tied to row operations because that would require way too much replicated logic; this ECC is only checked during a read operation and corrections are not automatically written back.
Then the data bus has completely independent self generated 32/40 ECC. I have not been able to find any details about how DDR5 implements end to end ECC but my guess is that 4 or 8 more bits are added with more chips which replace the self generated ECC that protects the data bus.
> Doug S (foo.delete@this.bar.bar) on April 5, 2021 6:57 am wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on April 4, 2021 8:45 pm wrote:
> > > This also means that the external overhead of ECC is greater going from 64/72 to 32/40,
> > > but maybe the internal organization is different for the mandatory internal ECC.
> >
> >
> > Given that full ECC for DDR5 will (at least) double the ECC DIMM price penalty I wouldn't be
> > surprised to see some using DDR5's internal ECC as an excuse to drop board support for it. Fewer
> > customers will demand it due to the higher cost, and marketing will be telling those customers
> > "its built into the DIMMs now, you don't need ECC except at the extreme high end".
> >
> > Less demand for it will mean those ECC DIMMs have an even greater price penalty above the 25%
> > raw cost than DDR4 ECC is above the 12.5% raw cost, which is why I should "at least" above.
> >
> > DDR5's internal ECC is 128 bits wide, so the bit penalty is kept pretty low.
>
> There is no cost difference.
>
> Anyway, everybody today read the entire cacheline, that is 512 bits
> with the extra 64 bits for ECC, that doesn't change with DDR5.
Transfers are done in 64 byte or 512 bit cache line sized chunks, but ECC is implemented on 128/144 or 256/288 words. 512/576 could be done but I have never seen it. The larger words have the advantage of supporting x4 chipkill and such improvements.
For DDR5 the internal ECC is 128/136 which can only correct single bit errors, and it is *not* tied to row operations because that would require way too much replicated logic; this ECC is only checked during a read operation and corrections are not automatically written back.
Then the data bus has completely independent self generated 32/40 ECC. I have not been able to find any details about how DDR5 implements end to end ECC but my guess is that 4 or 8 more bits are added with more chips which replace the self generated ECC that protects the data bus.