By: Robert Williams (crispysilicon.delete@this.gmail.com), April 7, 2021 11:05 am
Room: Moderated Discussions
wumpus (wumpus.delete.delete.delete@this.this.this.lost.in.a.hole) on April 7, 2021 9:10 am wrote:
> Doug S (foo.delete@this.bar.bar) on March 26, 2021 9:52 am wrote:
> > Brett (ggtgp.delete@this.yahoo.com) on March 25, 2021 5:17 pm wrote:
> > > Jon Masters (jcm.delete@this.jonmasters.org) on March 23, 2021 3:31 pm wrote:
> > > > The "Intel Unleashed" event this afternoon featured the announcement of
> > > > a new "IDM 2.0" model including a second attempt at doing a foundry:
> > > >
> > > > https://www.anandtech.com/show/16573/intels-new-strategy-20b-for-two-fabs-meteor-lake-7nm-tiles-new-foundry-services-ibm-collaboration-return-of-idf
> > >
> > > Intel’s unit growth is weak and each shrink is reducing die size by perhaps a third.
> > > So where does Intel possibly need 20 billion in new fabs when a shrink should close fabs?
> > >
> > > At 5nm you can put 256 cores on a chip but DDR cannot possibly feed these chips.
> > >
> > > I am predicting RAM goes on chip perhaps being called L4, and DRAM if included is used much
> > > like SSD’s for paging. Going from server chiplets to reticle limited dies with the bulk
> > > of the area RAM of some type and CPU’s along two edges with a slight gap in the middle
> > > so dies can be split in half for gamer chips. This would use 20 billion in fab space.
> > >
> >
> >
> > The "256 cores on a chip" market is just a niche, that does not affect the vast majority of the market
> > that will never have that many (CPU) cores no matter how large the transistor budget becomes.
> >
> > In that rareified air of extreme hyperscalers they are already going custom, they can create chips
> > with 10,000 pins to allow a couple dozen DRAM channels if that's what it takes to keep it fed.
> > They can solder the RAM stacks on both sides of their custom boards. They can do something like
> > HBM if it provides a better option (not sure there, since they care so much about power)
>
> Nvidia's Tesla boards use HBM, and are about as hyperscaler as you can get (and
> stay mass production). It seems the logical path once you get to those levels.
https://cdn.wccftech.com/wp-content/uploads/2020/10/Sapphire-Rapids-Intel-MCM-Design-1.png
Hybrid approach seems to be the ticket for now.
> Doug S (foo.delete@this.bar.bar) on March 26, 2021 9:52 am wrote:
> > Brett (ggtgp.delete@this.yahoo.com) on March 25, 2021 5:17 pm wrote:
> > > Jon Masters (jcm.delete@this.jonmasters.org) on March 23, 2021 3:31 pm wrote:
> > > > The "Intel Unleashed" event this afternoon featured the announcement of
> > > > a new "IDM 2.0" model including a second attempt at doing a foundry:
> > > >
> > > > https://www.anandtech.com/show/16573/intels-new-strategy-20b-for-two-fabs-meteor-lake-7nm-tiles-new-foundry-services-ibm-collaboration-return-of-idf
> > >
> > > Intel’s unit growth is weak and each shrink is reducing die size by perhaps a third.
> > > So where does Intel possibly need 20 billion in new fabs when a shrink should close fabs?
> > >
> > > At 5nm you can put 256 cores on a chip but DDR cannot possibly feed these chips.
> > >
> > > I am predicting RAM goes on chip perhaps being called L4, and DRAM if included is used much
> > > like SSD’s for paging. Going from server chiplets to reticle limited dies with the bulk
> > > of the area RAM of some type and CPU’s along two edges with a slight gap in the middle
> > > so dies can be split in half for gamer chips. This would use 20 billion in fab space.
> > >
> >
> >
> > The "256 cores on a chip" market is just a niche, that does not affect the vast majority of the market
> > that will never have that many (CPU) cores no matter how large the transistor budget becomes.
> >
> > In that rareified air of extreme hyperscalers they are already going custom, they can create chips
> > with 10,000 pins to allow a couple dozen DRAM channels if that's what it takes to keep it fed.
> > They can solder the RAM stacks on both sides of their custom boards. They can do something like
> > HBM if it provides a better option (not sure there, since they care so much about power)
>
> Nvidia's Tesla boards use HBM, and are about as hyperscaler as you can get (and
> stay mass production). It seems the logical path once you get to those levels.
https://cdn.wccftech.com/wp-content/uploads/2020/10/Sapphire-Rapids-Intel-MCM-Design-1.png
Hybrid approach seems to be the ticket for now.
