sr (nobody.delete@this.nowhere.com) on April 3, 2021 2:33 pm wrote:
> Anon (no.delete@this.spam.com) on April 3, 2021 2:08 pm wrote:
> > So, you are arguing in the case of transaction memory to
> > replace a ReaderWriterLock in a read intensive case?
>
> Yeah I forget that also if some other core modifies data accessed in transaction transaction also
> needs to fail. So hardware have to keep both transaction reads and writes in book to fail transaction
> if some other core access to modified or modifies line that is read on transaction.
>
> But yes, other cores are free to read lines that don't get modified on transaction. Transaction buffers
> writes and only distributes them after all are completed and old lines invalidated. After transaction
> success all writes are distributed atomically by hardware. It is a fine concept, of course it much
> easier to present idea than made it working with hardware where Intel has had some problems.
>
> And as I see it ARM copied Intel TSX as it is. Maybe they got some patent problems by doing so?

I think you're getting your history a bit mixed up. There's been a few different versions and Intel's is about the latest before ARM not the earliest. IBM's mainframe version even has some work to cope with them operating on the same data at the same time, now that deserves a patent if anything does!