By: Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr), April 13, 2021 12:01 am
Room: Moderated Discussions
Aspect of Anonimity (aoa.delete@this.pgsogcuei.com) on April 12, 2021 7:29 pm wrote:
> Maybe HW can implement something to make locking more efficient, and we need to
> turn to programming languages for an elegant solution to concurrency woes.
I wonder if it would be useful to have an area of fast memory (SRAM) inside the chip, accessed by all cores without cache, to implement locking for restricted parts (i.e. kernel only, due to the size limit).
For instance 64 Kbytes of MSR common to all cores inside a physical chip to store Mutexes?
No more problems due to the Mutex being stored into different core caches, with different MESI states.
It would not solve multi-socket systems, nor massively parallel applications, but might improve the standard case?
> Maybe HW can implement something to make locking more efficient, and we need to
> turn to programming languages for an elegant solution to concurrency woes.
I wonder if it would be useful to have an area of fast memory (SRAM) inside the chip, accessed by all cores without cache, to implement locking for restricted parts (i.e. kernel only, due to the size limit).
For instance 64 Kbytes of MSR common to all cores inside a physical chip to store Mutexes?
No more problems due to the Mutex being stored into different core caches, with different MESI states.
It would not solve multi-socket systems, nor massively parallel applications, but might improve the standard case?
