By: Dan Fay (daniel.fay.delete@this.gmail.com), April 13, 2021 12:03 pm
Room: Moderated Discussions
Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on April 13, 2021 1:01 am wrote:
> Aspect of Anonimity (aoa.delete@this.pgsogcuei.com) on April 12, 2021 7:29 pm wrote:
> > Maybe HW can implement something to make locking more efficient, and we need to
> > turn to programming languages for an elegant solution to concurrency woes.
>
> I wonder if it would be useful to have an area of fast memory (SRAM) inside the chip, accessed by all cores
> without cache, to implement locking for restricted parts (i.e. kernel only, due to the size limit).
> For instance 64 Kbytes of MSR common to all cores inside a physical chip to store Mutexes?
> No more problems due to the Mutex being stored into different core caches, with different MESI states.
> It would not solve multi-socket systems, nor massively parallel
> applications, but might improve the standard case?
>
FWIW, the dual-core STM32H7 microcontrollers have a series of hardware semaphores. It looks like the hardware semaphore block can notify one of the cores when a semaphore is freed via an interrupt.
https://www.st.com/content/ccc/resource/training/technical/product_training/group0/2a/6a/df/e1/3b/52/48/b7/STM32H7-System-Hardware_Semaphore_HSEM/files/STM32H7-System-Hardware_Semaphore_HSEM.pdf/_jcr_content/translations/en.STM32H7-System-Hardware_Semaphore_HSEM.pdf
> Aspect of Anonimity (aoa.delete@this.pgsogcuei.com) on April 12, 2021 7:29 pm wrote:
> > Maybe HW can implement something to make locking more efficient, and we need to
> > turn to programming languages for an elegant solution to concurrency woes.
>
> I wonder if it would be useful to have an area of fast memory (SRAM) inside the chip, accessed by all cores
> without cache, to implement locking for restricted parts (i.e. kernel only, due to the size limit).
> For instance 64 Kbytes of MSR common to all cores inside a physical chip to store Mutexes?
> No more problems due to the Mutex being stored into different core caches, with different MESI states.
> It would not solve multi-socket systems, nor massively parallel
> applications, but might improve the standard case?
>
FWIW, the dual-core STM32H7 microcontrollers have a series of hardware semaphores. It looks like the hardware semaphore block can notify one of the cores when a semaphore is freed via an interrupt.
https://www.st.com/content/ccc/resource/training/technical/product_training/group0/2a/6a/df/e1/3b/52/48/b7/STM32H7-System-Hardware_Semaphore_HSEM/files/STM32H7-System-Hardware_Semaphore_HSEM.pdf/_jcr_content/translations/en.STM32H7-System-Hardware_Semaphore_HSEM.pdf