By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), April 13, 2021 11:43 pm
Room: Moderated Discussions
Dan Fay (daniel.fay.delete@this.gmail.com) on April 13, 2021 12:03 pm wrote:
> FWIW, the dual-core STM32H7 microcontrollers have a series of hardware semaphores. It looks like the
> hardware semaphore block can notify one of the cores when a semaphore is freed via an interrupt.
Those type of semaphores are typically used to provide synchronization mechanisms between non-cache coherent cores and sometimes even different ones (e.g. the CPU core of a SoC and the GPU command/control core).
> FWIW, the dual-core STM32H7 microcontrollers have a series of hardware semaphores. It looks like the
> hardware semaphore block can notify one of the cores when a semaphore is freed via an interrupt.
Those type of semaphores are typically used to provide synchronization mechanisms between non-cache coherent cores and sometimes even different ones (e.g. the CPU core of a SoC and the GPU command/control core).