By: juanrga (nomail.delete@this.juanrga.com), April 11, 2021 4:38 am
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on April 9, 2021 9:23 am wrote:
> juanrga (nomail.delete@this.juanrga.com) on April 9, 2021 3:56 am wrote:
> > Ronald Maas (ronaldjmaas.delete@this.gmail.com) on April 8, 2021 9:25 am wrote:
> > > juanrga (nomail.delete@this.juanrga.com) on April 7, 2021 7:36 am wrote:
> > > >
> > > >
> > > >
> > >
> > > x86 cores are designed to be able to run at much higher frequencies compared to ARM cores. I
> > > think that largely explains the 20% - 30% difference in die area. In modern high performance
> > > cores the ISA does not have much impact anymore in either die area, absolute performance, or
> > > performance / Watt as modern x86 CPUs execute RISC-like micro-ops most of the time anyway.
> >
> > When comparing A64 vs x86, the tax is not only a RISC vs CISC difference.
> > A64 has additional advantages beyond a simpler decoding.
> >
> Of cause A64 has advantages over x86. But how much does these advantages translate these
> advantages to die area, absolute performance, or performance / Watt? My guess somewhere
> between 5% and 10%. And the main reason is x86 decoding is out of the critical path anyway
> as the majority of executed instructions are coming from the micro-op cache.
Simpler decoder, 3 operand, larger number of architectural registers... all that together implies a smaller number of transistors for doing the same work.
> Just look at an annotated die shot of any modern CPU core like Ryzen. Decoding
> block takes about 10% of the area. Maybe for N1 that area will be 5% (my ballpark
> guess). So yeah, there you have it as x86 tax translates to a 5% bigger die.
Does that area count just the decoders or does it also include the microcode ROM?
> juanrga (nomail.delete@this.juanrga.com) on April 9, 2021 3:56 am wrote:
> > Ronald Maas (ronaldjmaas.delete@this.gmail.com) on April 8, 2021 9:25 am wrote:
> > > juanrga (nomail.delete@this.juanrga.com) on April 7, 2021 7:36 am wrote:
> > > >
Just to give you an idea, in the previous generation,
> > > > if you look at ThunderX2, compared to AMD or Skylake,
> > > > for the same process node technology [we get] roughly 20%
> > > > to 25% smaller die area. That translates into lower
> > > > power. When we move to 7nm with ThunderX3, our core compared to AMD Rome’s 7nm is roughly 30% smaller.
> > > >
> > > >
> > >
> > > x86 cores are designed to be able to run at much higher frequencies compared to ARM cores. I
> > > think that largely explains the 20% - 30% difference in die area. In modern high performance
> > > cores the ISA does not have much impact anymore in either die area, absolute performance, or
> > > performance / Watt as modern x86 CPUs execute RISC-like micro-ops most of the time anyway.
> >
> > When comparing A64 vs x86, the tax is not only a RISC vs CISC difference.
> > A64 has additional advantages beyond a simpler decoding.
> >
> Of cause A64 has advantages over x86. But how much does these advantages translate these
> advantages to die area, absolute performance, or performance / Watt? My guess somewhere
> between 5% and 10%. And the main reason is x86 decoding is out of the critical path anyway
> as the majority of executed instructions are coming from the micro-op cache.
Simpler decoder, 3 operand, larger number of architectural registers... all that together implies a smaller number of transistors for doing the same work.
> Just look at an annotated die shot of any modern CPU core like Ryzen. Decoding
> block takes about 10% of the area. Maybe for N1 that area will be 5% (my ballpark
> guess). So yeah, there you have it as x86 tax translates to a 5% bigger die.
Does that area count just the decoders or does it also include the microcode ROM?
