Hello,

Anon (no.delete@this.spam.com) on April 16, 2021 4:51 pm wrote:
> LoongShot (Lsx.delete@this.lasx.com) on April 16, 2021 3:01 pm wrote:
> > Big week for ISAs - LoongArch
>
> Will it be another boring RISC?

I did some digging into this, as I maintain the MIPS64 port in Alpine, and was planning to target Loongson at some point.

From what I can tell, LoongArch is just a fork of the MIPS ISA, in a similar way to how MIPS32r5 and MIPS64r6 are backward-incompatible forks of the MIPS ISA. I conclude this based on the fact that LoongArch offers the same extensions that MIPS CPUs do, just with slightly different names, as can be seen in this translated press release. For example, what MIPS CPUs call the Virtualization Extension (VZ), LoongArch calls the LoongArch Virtualization Extension (LVZ). Another example is that the MIPS SIMD instructions (MSA) are renamed to LoongArch Vector Extension (LSX).

Specifically, I believe LoongArch to be a fork of MIPS64r6. If you look at the unofficial programmer's documentation, there are a lot of similarities, notably the removal of the delay slot and all instructions related to delayed branching using the delay slot.

So, most likely LoongArch is just a fork of MIPS64r6. Perhaps it is even just a branded version of MIPS64r6. Without seeing the bytecode emitted by an assembler for LoongArch, I can't know for sure.