Phenom TLB bug

By: Heikki Kultala (heikk.i.kultal.a.delete@this.gmail.com), May 6, 2021 12:46 pm
Room: Moderated Discussions
wumpus (wumpus.delete@this.lost.in.a.hole) on May 6, 2021 9:06 am wrote:
> Chester (lamchester.delete@this.gmail.com) on May 5, 2021 6:45 pm wrote:
> > > > Assuming you still want to keep "L1 "way size" = page size, that gives you
> > > > 8 cachelines per "way". I think once ARM made a 32-way L1 cache that they
> > > > claimed it was faster as 32-way, but that was certainly the exception.
> > > >
> > > > Do you want "60-way" caches?
> > >
> > > No.
> > >
> > > > Add some sort of inital TLB lookup to the L1 latency
> > > > (which of course would require more entries, because smaller pages)?
> > >
> > > I don't know what your question is.
> >
> > I think that refers to VIPT caches, where way size = page size is natural?
> >
> > But K10 got 3 cycle latency with a 64K 2-way L1D, so clearly way size = page size isn't the only way to go.
> >
>
> True, but I have to assume that they looked up the TLB first. And you'd need a
> bigger TLB than K10 if you had 512B pages instead of 4k pages. You could pull
> 16 values, but that wouldn't be any easier than just going to a 16 way cache.
>
> Or possibly they went a step beyond a "way picker" that would predict which page the value was on without the
> full TLB. If so, they never seemed to use it again (with the possible exception of instruction caches).
>
> way size = page size is an extremely good fit, and the exceptions don't seem to repeat.
> I'll note that the early Phenom had a nasty TLB bug (patching it took a performance hit),
> which might make AMD wary of putting the TLB in such a critical part of the path.

The TLB bug of Phenom was only related to TLB fills from caches. It had nothing to do with TLB hits.

I don't remember the exact details but It was something like cache coherency being broken for cached page tables.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
4K pages probably used to be too largeYuhong Bao2021/05/01 01:01 PM
  HDD seek time isn't freeMark Roulo2021/05/01 02:12 PM
    HDD seek time isn't freeYuhong Bao2021/05/01 02:21 PM
      HDD seek time isn't freeTim Mc2021/05/01 02:42 PM
        HDD seek time isn't freerwessel2021/05/01 02:57 PM
  4K pages probably used to be too largeBen LaHaise2021/05/02 10:45 AM
    VAX was 512 (in 1977) (NT)anonymous22021/05/02 08:36 PM
      FWIW, S/370 offered a choice of 2K and 4K (NT)rwessel2021/05/03 05:09 AM
      DEC's earliest PDP-11 disks were 512 (in 1971)John Yates2021/05/03 01:53 PM
    4K pages probably used to be too largeanon22021/05/03 01:17 AM
      4K pages probably used to be too largeBen LaHaise2021/05/03 05:36 PM
        Morotola 680x0 series page sizesBen LaHaise2021/05/03 05:51 PM
        4K pages probably used to be too largeanon22021/05/03 06:39 PM
          4K pages probably used to be too largeanon22021/05/03 08:51 PM
        4K pages probably used to be too largeYuhong Bao2021/05/03 10:51 PM
      4K pages probably used to be too largewumpus2021/05/05 09:06 AM
        4K pages probably used to be too largeanon22021/05/05 04:04 PM
          4K pages probably used to be too largeChester2021/05/05 06:45 PM
            4K pages probably used to be too largewumpus2021/05/06 09:06 AM
              Phenom TLB bugHeikki Kultala2021/05/06 12:46 PM
                Phenom TLB bugChester2021/05/06 05:29 PM
        4K pages probably used to be too largeEtienne Lorrain2021/05/06 01:08 AM
          4K pages probably used to be too largeJames2021/05/06 02:36 AM
            4K pages probably used to be too largerwessel2021/05/06 09:32 AM
              Reformatting SCSI disk sector sizeDoug S2021/05/06 11:30 AM
        4K pages probably used to be too largeDavid Hess2021/05/11 08:57 AM
  Page size is more complex/nuancedPaul A. Clayton2021/05/08 10:03 AM
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