Post looking at BTB behavior and size

By: Travis Downs (travis.downs.delete@this.gmail.com), May 10, 2021 8:59 pm
Room: Moderated Discussions
Anon (no.delete@this.spam.com) on May 10, 2021 4:43 pm wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on May 10, 2021 2:57 pm wrote:
> > Maybe it's just measurement error (e.g., due to turbo above
> > the expected frequency), or can Zen 3 really do this?
>
> I am not sure, but, what if, the uop cache works as a trace cache? I mean,
> if instructions across jmp instruction ends in the same uop cache line?
>
> Sounds as a perfectly valid optimizaion for me.

Yeah, it's an interesting idea: certainly the uop cache on Intel (and AMD seems similar) already has some mild aspects of a trace cache, e.g. sort of caching basic blocks rather than instructions (i.e., the target of a jump always starts a uop cache line, which means duplication if those instructions were already present in the middle of another line).
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TopicPosted ByDate
Post looking at BTB behavior and sizeTravis Downs2021/05/10 02:57 PM
  Post looking at BTB behavior and sizeAnon2021/05/10 04:43 PM
    Post looking at BTB behavior and sizeTravis Downs2021/05/10 08:59 PM
    Post looking at BTB behavior and sizeLinus Torvalds2021/05/11 10:13 AM
  RKL taken branch throughputChester2021/05/10 05:25 PM
    RKL taken branch throughputTravis Downs2021/05/10 09:00 PM
      RKL taken branch throughputChester2021/05/11 10:04 PM
        RKL taken branch throughputTravis Downs2021/05/14 10:34 PM
          RKL taken branch throughput---2021/05/15 10:07 AM
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