structured ASICs

By: David Kanter (dkanter.delete@this.realworldtech.com), May 11, 2021 6:08 am
Room: Moderated Discussions
Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on May 11, 2021 12:49 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on May 10, 2021 6:26 pm wrote:
> > I don't know how many of you saw this, but IBM recently announced that they have a gate-all-around process:
> >
> > https://www.cnet.com/news/ibm-nanosheets-promise-better-speed-and-battery-life-for-next-gen-chips/
> >
> > I spent a bit of time talking with Stephen and I think he captured the situation well.
> >
> > It's clear that Intel, Samsung, and TSMC already have Gate all around processes under
> > developement. IBM has completed the research phase, but they don't do their own production
> > any more and GF has kind of given up. So they need to find a customer.
> >
> > I'm not sure who would be interested. The memory folks will have a very different process flow and
> > may not need GAA for years. SMIC probably wouldn't be allowed to license. Who else is out there?
> >
> > I'm curious about the dielectric underneath, I'm hoping we will see a VLSI or IEDM paper on this.
> >
> > David
>
> Completely candid question, just software engineer here...
> Would it be possible for a big company (big investment) to produce a chip "full of transistors", i.e. a regular
> pattern - but without connection in between those transistors - and then for a smaller company (smaller investment)
> to rework the chip by adding the wires, only adding conducting material, to produce what they need?
> I understand all transistors are not equals; power, clocks and data wires may be different,
> and that solutions for wires crossing should be designed, but it would probably be
> a lot better than FPGAs - maybe reaching current processor performance?
> What are the main problems with this approach?

That's what's called a structured ASIC and was largely done by eASIC, now owned by Intel!

David
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
IBM's "2nm" Gate-all-around - will it matter?David Kanter2021/05/10 05:26 PM
  IBM's "2nm" Gate-all-around - will it matter?John H2021/05/10 06:20 PM
  IBM's "2nm" Gate-all-around - will it matter?Mark Roulo2021/05/10 06:55 PM
  IBM's "2nm" Gate-all-around - will it matter?Anon2021/05/10 08:08 PM
  IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/10 09:34 PM
  IBM's "2nm" Gate-all-around - will it matter?Etienne Lorrain2021/05/10 11:49 PM
    IBM's "2nm" Gate-all-around - will it matter?David Hess2021/05/11 04:05 AM
    structured ASICsDavid Kanter2021/05/11 06:08 AM
    IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/11 07:05 AM
      IBM's "2nm" Gate-all-around - will it matter?Kester L2021/05/11 07:22 AM
        IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/11 10:31 AM
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