IBM's "2nm" Gate-all-around - will it matter?

By: Adrian (a.delete@this.acm.org), May 11, 2021 7:05 am
Room: Moderated Discussions
Etienne Lorrain (etienne_lorrain.delete@this.yahoo.fr) on May 11, 2021 12:49 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on May 10, 2021 6:26 pm wrote:
> > I don't know how many of you saw this, but IBM recently announced that they have a gate-all-around process:
> >
> > https://www.cnet.com/news/ibm-nanosheets-promise-better-speed-and-battery-life-for-next-gen-chips/
> >
> > I spent a bit of time talking with Stephen and I think he captured the situation well.
> >
> > It's clear that Intel, Samsung, and TSMC already have Gate all around processes under
> > developement. IBM has completed the research phase, but they don't do their own production
> > any more and GF has kind of given up. So they need to find a customer.
> >
> > I'm not sure who would be interested. The memory folks will have a very different process flow and
> > may not need GAA for years. SMIC probably wouldn't be allowed to license. Who else is out there?
> >
> > I'm curious about the dielectric underneath, I'm hoping we will see a VLSI or IEDM paper on this.
> >
> > David
>
> Completely candid question, just software engineer here...
> Would it be possible for a big company (big investment) to produce a chip "full of transistors", i.e. a regular
> pattern - but without connection in between those transistors - and then for a smaller company (smaller investment)
> to rework the chip by adding the wires, only adding conducting material, to produce what they need?
> I understand all transistors are not equals; power, clocks and data wires may be different,
> and that solutions for wires crossing should be designed, but it would probably be
> a lot better than FPGAs - maybe reaching current processor performance?
> What are the main problems with this approach?


As others have already replied, this has been done, especially during the seventies and the eighties of last century.

The most used products were the gate arrays, where you had an array of unconnected logic gates and you designed the metallization masks for their interconnections.

Many of the ancient large computers and supercomputers were made with such gate arrays.

The gate arrays were killed for small series products by the FPGAs and for high-volume products by the completely custom integrated circuits, which are nonetheless designed using a library of standard gates, so the design effort is not much higher than for a gate array, but the flexibility of choosing and placing in the array different variants of gates and of other logic cells allows a much higher performance and much less wasted area than when starting with a fixed gate array.

Modern circuits have a large number of interconnection masks, so the cost for the interconnection masks might be at least a third but more likely a half of the total mask set costs, so the economies for a using fixed gate array would be much less today than 40 years ago, when the interconnection masks might have been only 10% of the cost of a mask set.

While the gate arrays used for logic circuits have been the main product of this type, there were a few companies, including one where I have worked, which offered as set of chips of different complexities, for analog devices, which included arrays of transistors of several different sizes, in thermally matched pairs, and areas with various other analog components, e.g. resistors, capacitors, reference voltages.

So you could really design any IC by designing the interconnections. Still the problems were sub-optimal performance due to lack of layout optimization and the difficulty of succeeding to use a high percentage of the resources existing in a given chip.

I do not think that there is much future in the revival of such techniques.
What is needed now is to have more options for lower-cost multi-project wafer shuttles, like those sponsored now by Google at SkyWater Technology.

Anyone can design a complex custom integrated circuit on their laptop, the problem is its fabrication at an acceptable cost in the case when you only need a few hundreds or a few thousands at most.

The way to reduce the manufacturing costs to an acceptable level is to share them with hundreds of other customers, by having mask sets and processed wafers in common with everybody.

































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TopicPosted ByDate
IBM's "2nm" Gate-all-around - will it matter?David Kanter2021/05/10 05:26 PM
  IBM's "2nm" Gate-all-around - will it matter?John H2021/05/10 06:20 PM
  IBM's "2nm" Gate-all-around - will it matter?Mark Roulo2021/05/10 06:55 PM
  IBM's "2nm" Gate-all-around - will it matter?Anon2021/05/10 08:08 PM
  IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/10 09:34 PM
  IBM's "2nm" Gate-all-around - will it matter?Etienne Lorrain2021/05/10 11:49 PM
    IBM's "2nm" Gate-all-around - will it matter?David Hess2021/05/11 04:05 AM
    structured ASICsDavid Kanter2021/05/11 06:08 AM
    IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/11 07:05 AM
      IBM's "2nm" Gate-all-around - will it matter?Kester L2021/05/11 07:22 AM
        IBM's "2nm" Gate-all-around - will it matter?Adrian2021/05/11 10:31 AM
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